八路智能搶答器的設(shè)計(jì)單片機(jī)畢業(yè)設(shè)計(jì)外文翻譯單片機(jī)AT89C51

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1、 AT89C51 Features ? Compatible with MCS-51? Products ? 4K Bytes of In-System Reprogrammable Flash Memory ? Endurance: 1,000 Write/Erase Cycles ? Fully Static Operation: 0 Hz to 24 MHz ? Three-level Program Memory Lock ? 128 x 8-bit Internal RAM ? 32 Programmable I/O Lines ? Two 16-bit Time

2、r/Counters ? Six Interrupt Sources ? Programmable Serial Channel ? Low-power Idle and Power-down Modes Description The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4Kbytes of Flash programmable and erasable read only memory (PEROM). The deviceis manufactured using Atme

3、l’s high-density nonvolatile memory technology and iscompatible with the industry-standard MCS-51 instruction set and pinout. The on-chipFlash allows the program memory to be reprogrammed in-system or by a conventionalnonvolatile memory programmer. By combining a versatile 8-bit CPU with Flashon a m

4、onolithic chip, the Atmel AT89C51 is a powerful microcomputer which providesa highly-flexible and cost-effective solution to many embedded control applications.The AT89C51 provides the following standard features: 4Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bittimer/counters, a five vec

5、tor two-level interrupt architecture,a full duplex serial port, on-chip oscillator and clock circuitry.In addition, the AT89C51 is designed with static logicfor operation down to zero frequency and supports twosoftware selectable power saving modes. The Idle Modestops the CPU while allowing the RAM,

6、 timer/counters,serial port and interrupt system to continue functioning. ThePower-down Mode saves the RAM contents but freezesthe oscillator disabling all other chip functions until the nexthardware reset. Pin Configurations Pin Description VCC：Supply voltage. GND：Ground. Port 0：Port 0 is a

7、n 8-bit open-drain bi-directional I/O port. As anoutput port, each pin can sink eight TTL inputs. When 1sare written to port 0 pins, the pins can be used as highimpedanceinputs. Port 0 may also be configured to be the multiplexed loworderaddress/data bus during accesses to external programand data

8、memory. In this mode P0 has internalpullups. Port 0 also receives the code bytes during Flash programming,and outputs the code bytes during programverification. External pullups are required during program verification. Port 1：Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Po

9、rt 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high bythe internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 1 also receives the

10、low-order address bytes during Flash programming and verification. Port 2：Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inp

11、uts. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this

12、application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.Port 2 also receives the high-order address bits and some control signals during Flash programmin

13、g and verification. Port 3：Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally

14、being pulled low will source current (IIL) because of the pullups.Port 3 also serves the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for Flash programming and verification. ALE/PROG：Address Latch Enable output pulse for latchin

15、g the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming.In normal operation ALE is emitted at a constant rate of 1/6the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, th

16、at one ALE pulse is skipped during each access to external Data Memory.If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no

17、effect if the microcontroller is in external execution mode. PSEN：Program Store Enable is the read strobe to external program memory.When the AT89C51 is executing code from external programmemory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each a

18、ccess to external data memory. EA/VPP：External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA shou

19、ld be strapped to VCC for internal program executions. This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming, for parts that require 12-volt VPP. XTAL1：Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2：Output

20、 from the inverting oscillator amplifier. Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively,of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive t

21、he device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and max

22、imum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this

23、mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution,from where it left off, up to two machine cycles before the internal reset algorithm takes contro

24、l. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a

25、port pin or to external memory. Figure 1. Oscillator Connections Figure 2. External Clock Drive Configuration Power-down Mode In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function

26、 Registers retain their values until the power-down mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long

27、 enough to allow the oscillator to restart and stabilize. Program Memory Lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is

28、 sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to fun

29、ction properly. Programming the Flash The AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The lo

30、w-voltage programming mode provides a convenient way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers. The AT89C51 is shipped with either the high-voltage or low-voltage programming mode ena

31、bled. The AT89C51 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. AT89C51 主要性能參數(shù)：

32、l 與MCS-51產(chǎn)品指令系統(tǒng)完全兼容 l 4K字節(jié)可重檫寫(xiě)Flash閃速存儲(chǔ)器 l 1000次檫寫(xiě)周期 l 全靜態(tài)操作：0HZ-24MHZ l 三級(jí)加密程序存儲(chǔ)器 l 128*8字節(jié)內(nèi)部RAM l 32個(gè)可編程I/O口線 l 2個(gè)16位定時(shí)/記數(shù)器 l 6個(gè)中斷源 l 可編程串行UART通道 l 低功耗空閑和掉電模式 功能特性概述： AT89C51提供以下標(biāo)準(zhǔn)功能：4K字節(jié)Flash閃速存儲(chǔ)器，128字節(jié)內(nèi)部RAM，32個(gè)I/O口線，兩個(gè)16位定時(shí)/記數(shù)器，一個(gè)5向量?jī)杉?jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振蕩器及時(shí)鐘電路。同時(shí)，AT89C51可降至0HZ的靜態(tài)邏輯操

33、作，并支持兩種軟件可選的節(jié)電工作模式?？臻e方式停止CPU的工作，但允許RAM，定時(shí)/記數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作直到下一個(gè)硬件復(fù)位。 AT89C51是美國(guó)ATMEL公司生產(chǎn)的低電壓，高性能CMOS的8位單片機(jī)，片內(nèi)含4k bytes的可反復(fù)擦寫(xiě)的只讀程序存儲(chǔ)器（PEROM）和128 bytes的隨機(jī)存取數(shù)據(jù)存儲(chǔ)器（RAM），器件采用ATMEL公司的高密度、非易失性存儲(chǔ)技術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn)MCS-51指令系統(tǒng)，片內(nèi)置通用8位中央處理器（CPU）和Flash存儲(chǔ)單元，功能強(qiáng)大AT89C51單片機(jī)可為您提供許多高性價(jià)比的應(yīng)用場(chǎng)合，可靈活應(yīng)用于各種

34、控制領(lǐng)域。 引腳功能說(shuō)明 Vcc：電源電壓 GND：地 P0 口：P0 口是一組8 位漏極開(kāi)路型雙向I／O 口，也即地址／數(shù)據(jù)總線復(fù)用口。作為輸出口用時(shí)，每位能吸收電流的方式驅(qū)動(dòng)8個(gè)TTL邏輯門(mén)電路，對(duì)端口寫(xiě)“1”可作為高阻抗輸入端用。在訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器或程序存儲(chǔ)器時(shí)，這組口線分時(shí)轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總線復(fù)用，在訪問(wèn)期間激活內(nèi)部上拉電阻。在FIash編程時(shí)，P0口接收指令字節(jié)，而在程序校驗(yàn)時(shí)，輸出指令字節(jié)，校驗(yàn)時(shí)，要求外接上拉電阻。 P1口：P1是一個(gè)帶內(nèi)部上拉電阻的8位雙向I／O口，P1的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門(mén)電路。對(duì)端口寫(xiě)“1”，通過(guò)內(nèi)部的上

35、拉電阻把端口拉到高電平，此時(shí)可作輸入口。作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。FIash編程和程序校驗(yàn)期間，P1接收低8位地址。 P2口：P2是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I／O口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯門(mén)電路。對(duì)端口寫(xiě)“1”，通過(guò)內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口，作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。在訪問(wèn)外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVX@DPTR指令）時(shí)，P2口送出高8位地址數(shù)據(jù)。在訪問(wèn)8 位地址的外部數(shù)據(jù)存儲(chǔ)器（

36、如執(zhí)行MOVX@RI 指令）時(shí)，P2 口線上的內(nèi)容（也即特殊功能寄存器（SFR）區(qū)中R2寄存器的內(nèi)容），在整個(gè)訪問(wèn)期間不改變。Flash編程或校驗(yàn)時(shí)，P2亦接收高位地址和其它控制信號(hào) P3口：P3口是一組帶有內(nèi)部上拉電阻的8 位雙向I／O 口。P3 口輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4 個(gè)TTL邏輯門(mén)電路。對(duì)P3 口寫(xiě)入“1”時(shí)，它們被內(nèi)部上拉電阻拉高并可作為輸入端口。作輸入端時(shí)，被外部拉低的P3 口將用上拉電阻輸出電流（IIL）。 P3口除了作為一般的I／O口線外，更重要的用途是它的第二功能，如下表所示： P3.0 RXD（串行輸入口） P3.1 TXD（串行輸出口） P

37、3.2 INT0（外中斷0） P3.3 INT1（外中斷1） P3.4 T0（定時(shí)/計(jì)數(shù)器0外部輸入） P3.5 T1（定時(shí)/計(jì)數(shù)器1外部輸入） P3.6 WR（外部數(shù)據(jù)存儲(chǔ)器寫(xiě)選通） P3.7 RD（外部數(shù)據(jù)存儲(chǔ)器讀選通） P3口還接收一些用于Flash閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。 RST：復(fù)位輸入。當(dāng)振蕩器工作時(shí)，RST引腳出現(xiàn)兩個(gè)機(jī)器周期以上高電平將使單片機(jī)復(fù)位。 ALE／PROG： 當(dāng)訪問(wèn)外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問(wèn)外部存儲(chǔ)器，ALE 仍以時(shí)鐘振蕩頻率的l／6 輸出固定的正脈沖信號(hào)，

38、因此它可對(duì)外輸出時(shí)鐘或用于定時(shí)目的。要注意的是：每當(dāng)訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過(guò)一個(gè)ALE脈沖。對(duì)Flash存儲(chǔ)器編程期間，該引腳還用于輸入編程脈沖（PROG）。如有必要，可通過(guò)對(duì)特殊功能寄存器（SFR）區(qū)中的8EH單元的DO 位置位，可禁止ALE 操作。該位置位后，只有一條MOVX和MOVC指令A(yù)LE才會(huì)被激活。此外，該引腳會(huì)被微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE無(wú)效。 PSEN：程序儲(chǔ)存允許（PSEN）輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)AT89C51 由外部程序存儲(chǔ)器取指令（或數(shù)據(jù)）時(shí)，每個(gè)機(jī)器周期兩次PSEN有效，即輸出兩個(gè)脈沖。在此期間，當(dāng)訪問(wèn)外部數(shù)據(jù)存儲(chǔ)器，這兩次有效的PS

39、EN信號(hào)出現(xiàn)。 EA／VPP：外部訪問(wèn)允許。欲使CPU僅訪問(wèn)外部程序存儲(chǔ)器（地址為0000H—FFFFH），EA端必須保持低電平（接地）。需注意的是：如果加密位LB1被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。如EA端為高電平（接VCC端），CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。Flash存儲(chǔ)器編程時(shí)，該引腳加上+12V的編程允許電源Vpp，當(dāng)然這必須是該器件是使用12V編程電壓Vpp。 XTAL1：振蕩器反相放大器的及內(nèi)部時(shí)鐘發(fā)生器的輸入端。 XTAL2：振蕩器反相放大器的輸出端。 時(shí)鐘振蕩器： AT89C5l 中有一個(gè)用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器，引腳XTAL1 和XTAL2 分別

40、是該放大器的輸入端和輸出端。這個(gè)放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構(gòu)成自激振蕩器，振蕩電路參見(jiàn)圖5。外接石英晶體（或陶瓷諧振器）及電容C1、C2接在放大器的反饋回路中構(gòu)成并聯(lián)振蕩電路。對(duì)外接電容C1、C2雖然沒(méi)有十分嚴(yán)格的要求，但電容容量的大小會(huì)輕微影響振蕩頻率的高低、振蕩器工作的穩(wěn)定性、起振的難易程序及溫度穩(wěn)定性，如果使用石英晶體，我們推薦電容使用30pF10pF，而如使用陶瓷諧振器建議選擇40pF10F。用戶也可以采用外部時(shí)鐘。采用外部時(shí)鐘的電路如圖5右圖所示。這種情況下，外部時(shí)鐘脈沖接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端，XTAL2則懸空。 圖1內(nèi)部振蕩電路圖

41、 2外部時(shí)鐘驅(qū)動(dòng)電路 石英晶體時(shí)：C1，C2＝30pF10pF 陶瓷濾波器：C1，C2＝40pF10pF 由于外部時(shí)鐘信號(hào)是通過(guò)一個(gè)2分頻觸發(fā)器后作為內(nèi)部時(shí)鐘信號(hào)的，所以對(duì)外部時(shí)鐘信號(hào)的占空比沒(méi)有特殊要求，但最小高電平持續(xù)時(shí)間和最大的低電平持續(xù)時(shí)間應(yīng)符合產(chǎn)品技術(shù)條件的要求。 空閑節(jié)電模式： AT89C51 有兩種可用軟件編程的省電模式，它們是空閑模式和掉電工作模式。這兩種方式是控制專(zhuān)用寄存器PCON（即電源控制寄存器）中的PD（PCON.1）和IDL（PCON.0）位來(lái)實(shí)現(xiàn)的。PD 是掉電模式，當(dāng)PD=1 時(shí)，激活掉電工作模式，單片機(jī)進(jìn)入掉電工作狀態(tài)。ID

42、L是空閑等待方式，當(dāng)IDL=1，激活空閑工作模式，單片機(jī)進(jìn)入睡眠狀態(tài)。如需同時(shí)進(jìn)入兩種工作模式，即PD和IDL同時(shí)為1，則先激活掉電模式。在空閑工作模式狀態(tài)，CPU保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時(shí)，片內(nèi)RAM和所有特殊功能寄存器的內(nèi)容保持不變?？臻e模式可由任何允許的中斷請(qǐng)求或硬件復(fù)位終止。終止空閑工作模式的方法有兩種，其一是任何一條被允許中斷的事件被激活，IDL（PCON.0）被硬件清除，即刻終止空閑工作模式。程序會(huì)首先響應(yīng)中斷，進(jìn)入中斷服務(wù)程序，執(zhí)行完中斷服務(wù)程序并緊隨RETI（中斷返回）指令后，下一條要執(zhí)行的指令就是使單片機(jī)進(jìn)入空閑模式那條指令后面的一條

43、指令。其二是通過(guò)硬件復(fù)位也可將空閑工作模式終止。需要注意的是，當(dāng)由硬件復(fù)位來(lái)終止空閑工作模式時(shí)，CPU 通常是從激活空閑模式那條指令的下一條指令開(kāi)始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬件復(fù)位脈沖要保持兩個(gè)機(jī)器周期（24個(gè)時(shí)鐘周期）有效，在這種情況下，內(nèi)部禁止CPU訪問(wèn)片內(nèi)RAM，而允許訪問(wèn)其它端口。為了避免可能對(duì)端口產(chǎn)生意外寫(xiě)入，激活空閑模式的那條指令后一條指令不應(yīng)是一條對(duì)端口或外部存儲(chǔ)器的寫(xiě)入指令。 掉電模式： 在掉電模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM 和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將重新

44、定義全部特殊功能寄存器但不改變RAM中的內(nèi)容，在Vcc恢復(fù)到正常工作電平前，復(fù)位應(yīng)無(wú)效，且必須保持一定時(shí)間以使振蕩器重啟動(dòng)并穩(wěn)定工作。 程序存儲(chǔ)器的加密： AT89C51 可使用對(duì)芯片上的3 個(gè)加密位LB1、LB2、LB3 進(jìn)行編程（P）或不編程（U）來(lái)得到如下表所示的功能加密位保護(hù)功能表： 當(dāng)加密位LB1 被編程時(shí)，在復(fù)位期間，EA端的邏輯電平被采樣并鎖存，如果單片機(jī)上電后一直沒(méi)有復(fù)位，則鎖存起的初始值是一個(gè)隨機(jī)數(shù)，且這個(gè)隨機(jī)數(shù)會(huì)一直保存到真正復(fù)位為止。為使單片機(jī)能正常工作，被鎖存的EA 電平值必須與該引腳當(dāng)前的邏輯電平一致。此外，加密位只能通過(guò)整片擦除的方法清除。 Flash閃速存

45、儲(chǔ)器的編程： AT89C51 單片機(jī)內(nèi)部有4k 字節(jié)的Flash PEROM，這個(gè)Flash 存儲(chǔ)陣列出廠時(shí)已處于擦除狀態(tài)（即所有存儲(chǔ)單元的內(nèi)容均為FFH），用戶隨時(shí)可對(duì)其進(jìn)行編程。編程接口可接收高電壓（+12V）或低電壓（Vcc）的允許編程信號(hào)。低電壓編程模式適合于用戶在線編程系統(tǒng)，而高電壓編程模式可與通用EPROM編程器兼容。AT89C51單片機(jī)中，有些屬于低電壓編程方式，而有些則是高電壓編程方式，用戶可從芯片上的型號(hào)和讀取芯片內(nèi)的名字節(jié)獲得該信息。 AT89C51的程序存儲(chǔ)器陣列是采用字節(jié)寫(xiě)入方式編程的，每次寫(xiě)入一個(gè)字節(jié)，要對(duì)整個(gè)芯片內(nèi)的PEROM程序存儲(chǔ)器寫(xiě)入一個(gè)非空字節(jié)，必須使用片擦除的方式將整個(gè)存儲(chǔ)器的內(nèi)容清除。 第13頁(yè) 共13頁(yè)