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1、2016Verilog 語(yǔ)言 實(shí)驗(yàn)報(bào)告專(zhuān) 業(yè)：計(jì)算機(jī)科學(xué)與技術(shù)班 級(jí)：CS1409學(xué) 號(hào)：U201414813姓 名：唐禮威電 話(huà)：15827505005郵 件：完成日期：2016.6.13華 中 科 技 大 學(xué) 課 程 實(shí) 驗(yàn) 報(bào) 告目 錄1數(shù)據(jù)通路實(shí)驗(yàn)11.1實(shí)驗(yàn)?zāi)康?1.2實(shí)驗(yàn)內(nèi)容及要求11.3實(shí)驗(yàn)方案21.4實(shí)驗(yàn)步驟21.5故障及分析21.6仿真與結(jié)果31.7心得與體會(huì)42FSM實(shí)驗(yàn)52.1實(shí)驗(yàn)?zāi)康?2.2實(shí)驗(yàn)內(nèi)容及要求52.3實(shí)驗(yàn)方案62.4實(shí)驗(yàn)步驟62.5故障及分析72.6仿真與結(jié)果72.7心得與體會(huì)83意見(jiàn)和建議94附錄1011 數(shù)據(jù)通路實(shí)驗(yàn)1.1 實(shí)驗(yàn)?zāi)康木C合應(yīng)用掌握的簡(jiǎn)單組合
2、電路和時(shí)序電路的設(shè)計(jì)方法，完成一個(gè)簡(jiǎn)單的數(shù)據(jù)通路的設(shè)計(jì)。1.2 實(shí)驗(yàn)內(nèi)容及要求1. 根據(jù)下圖給出的數(shù)據(jù)通路（圖中R0、R1和ACC是寄存器，+是加法器，其它則是多路選擇器），完成相應(yīng)的Verilog程序設(shè)計(jì)，圖中數(shù)據(jù)線(xiàn)的寬度為8位，要求可以擴(kuò)充至16位或者是32位；2. 根據(jù)下圖給出的數(shù)據(jù)通路（圖中SUM和NEXT是寄存器，Memory是存儲(chǔ)器，+是加法器，=0是比較器，其它則是多路選擇器），完成相應(yīng)的Verilog程序設(shè)計(jì)，圖中數(shù)據(jù)線(xiàn)的寬度為8位，要求可以擴(kuò)充至16位或者是32位。實(shí)驗(yàn)要求：程序必須自己編寫(xiě)，滿(mǎn)足數(shù)據(jù)通路設(shè)計(jì)要求，綜合結(jié)果正確。1.3 實(shí)驗(yàn)方案根據(jù)要求，先把選擇器、加法器、寄
3、存器、比較器和存儲(chǔ)器分模塊編寫(xiě)，在主模塊中根據(jù)數(shù)據(jù)通路調(diào)用即可。題目中要求數(shù)據(jù)線(xiàn)寬度為8位，并且可以擴(kuò)充至16位或32位，所以在前面定義WIDTH，利用parameter的參數(shù)傳遞功能來(lái)實(shí)現(xiàn)。1.4 實(shí)驗(yàn)步驟1.分模塊編寫(xiě)代碼（見(jiàn)附錄）2.運(yùn)行綜合Run Synthesis3.綜合成功后檢查RTL Analysis中的電路圖Schematic1.5 故障及分析剛開(kāi)始跑出來(lái)很多線(xiàn)是斷的，后來(lái)發(fā)現(xiàn)是引腳對(duì)應(yīng)部分的代碼沒(méi)有寫(xiě)完整。后來(lái)加法器和ACC的參數(shù)順序?qū)戝e(cuò)，導(dǎo)致接線(xiàn)與題給的不一致，發(fā)現(xiàn)問(wèn)題后及時(shí)改正了。1.6 仿真與結(jié)果Schematic圖形如下：第一個(gè)數(shù)據(jù)通路：第二個(gè)數(shù)據(jù)通路：由以上兩圖可得
4、，成功完成了要求的數(shù)據(jù)通路的設(shè)計(jì)，滿(mǎn)足了各基本器件的輸入輸出鏈接要求；改變數(shù)據(jù)線(xiàn)寬度后再檢查電路圖，發(fā)現(xiàn)數(shù)據(jù)線(xiàn)做出相應(yīng)改變，完成該實(shí)驗(yàn)。1.7 心得與體會(huì)對(duì)數(shù)據(jù)通路的設(shè)計(jì)有了更好的理解，明白了數(shù)據(jù)通路的基本器件構(gòu)成，熟悉了這些器件的功能和端口，掌握了Verilog完成基本運(yùn)算器件的設(shè)計(jì)，完成了數(shù)據(jù)通路的設(shè)計(jì)。 2 FSM實(shí)驗(yàn)2.1 實(shí)驗(yàn)?zāi)康恼莆沼肰erilog語(yǔ)言進(jìn)行FSM設(shè)計(jì)、實(shí)現(xiàn)和仿真的方法。2.2 實(shí)驗(yàn)內(nèi)容及要求5.1_1、用FSM實(shí)現(xiàn)一個(gè)mealy型序列檢測(cè)器，對(duì)一位的串行輸入序列中的“1”的數(shù)量進(jìn)行檢測(cè)。如果“1”的總數(shù)可以被3整除，輸出“1”，否則輸出“0”。5.1_2、用FSM實(shí)
5、現(xiàn)一個(gè)moore型序列檢測(cè)器，對(duì)兩位的串行輸入序列進(jìn)行檢測(cè)。輸入01,00時(shí)，輸出0，輸入11,00時(shí)，輸出1，輸入10,00時(shí)，輸出反向。5.1_3、用FSM實(shí)現(xiàn)一個(gè)計(jì)數(shù)器（采用存儲(chǔ)器），對(duì)一位的輸入進(jìn)行計(jì)數(shù)。計(jì)數(shù)序列為：000,001,011，101,111，010。5.2、用FSM實(shí)現(xiàn)一個(gè)序列識(shí)別器，該FSM的狀態(tài)轉(zhuǎn)移圖如下所示，它能夠?qū)σ晃坏拇休斎胄蛄兄械摹?”的數(shù)量進(jìn)行檢測(cè)。如果FSM發(fā)現(xiàn)輸入“1”的總數(shù)可以被3整除時(shí)，輸出“1”；否則，輸出“0”。同時(shí)針對(duì)“01011011101”輸入序列，寫(xiě)出相應(yīng)的仿真程序并進(jìn)行真波測(cè)試。2.3 實(shí)驗(yàn)方案先根據(jù)要求畫(huà)出狀態(tài)圖，根據(jù)狀態(tài)圖編寫(xiě)程序
6、，根據(jù)程序編寫(xiě)仿真程序，最后得出結(jié)果和結(jié)論。2.4 實(shí)驗(yàn)步驟5.1_1狀態(tài)圖：S1S0 in=1/1 in=1/0 in=0/0 in=1/0 in=1/0S4S3 in=0/0 in=1/1 in=0/05.1_2狀態(tài)圖：S0 in=00 in=01 in=10 in=11S2S1S3S6S5S4 in=00 in=00 in=00 out=0 out翻轉(zhuǎn) out=15.1_3狀態(tài)圖：1.根據(jù)以上狀態(tài)圖編寫(xiě)源程序（見(jiàn)附錄）2.運(yùn)行綜合Run Synthesis3.綜合正確后編寫(xiě)仿真程序4.仿真，得到仿真波形，驗(yàn)證結(jié)果2.5 故障及分析無(wú)故障2.6 仿真與結(jié)果5.1_1：如圖，1的個(gè)數(shù)是3的倍
7、數(shù)時(shí)輸出1與預(yù)期一致5.1_2：如圖，輸入01后再輸入00，輸出0；輸入11后再輸入00，輸出1；輸入10后再輸入00，輸出翻轉(zhuǎn)：與預(yù)期一致5.1_3：如圖，輸出序列為000,001,011,101,111,010（重復(fù)）與預(yù)期一致5.2：如圖，1的個(gè)數(shù)是3的倍數(shù)時(shí)輸出1與預(yù)期一致2.7 心得與體會(huì)這次實(shí)驗(yàn)通過(guò)FSM設(shè)計(jì)明白了設(shè)計(jì)的過(guò)程和步驟，首先要知道分為哪些狀態(tài)，設(shè)計(jì)的是何種電路，如何選擇用mealy還是moore型電路，狀態(tài)轉(zhuǎn)移要如何實(shí)現(xiàn)。知道了mealy型和moore型電路的區(qū)別：當(dāng)要求輸出對(duì)輸入快速響應(yīng)并希望電路簡(jiǎn)單時(shí)選擇mealy型，當(dāng)要求時(shí)序輸出穩(wěn)定，能接受輸出序列晚一個(gè)周期，即
8、選擇moore型電路不增加電路復(fù)雜性時(shí)，選擇moore型電路。3 意見(jiàn)和建議建議老師上課還是用中文PPT比較好，另外作業(yè)練習(xí)也用中文給出來(lái)，題目要求也盡量具體些，這樣會(huì)減少我們學(xué)習(xí)的成本，更加有效的學(xué)習(xí)這門(mén)課。4 附錄源程序：4.1（第一個(gè)數(shù)據(jù)通路）/主模塊module text4(S0,S1,S2,S3,Clk,reset,load,outR0,outR1,outACC,outS0,outS1,outS2,outS3,outA); parameter WIDTH=8; /位寬8位 input S0,S1,S2,S3,Clk,reset,load; output WIDTH-1:0 outR0
9、,outR1,outACC,outS0,outS1,outS2,outS3,outA; register #(8) R0(inR0,Clk,reset,load,outR0); register #(8) R1(inR1,Clk,reset,load,outR1); register #(8) ACC(inACC,Clk,reset,load,outACC); mux #(8) S0(S0,inS00,inS01,outS0); mux #(8) S1(S1,inS10,inS11,outS1); mux #(8) S2(S2,inS20,inS21,outS2); mux #(8) S3(S
10、3,inS30,inS31,outS3); add #(8) W1(inA0,inA1,outA); assign inS00=outS3; assign inS10=outS3; assign inS01=outR0; assign inS20=outR0; assign inS11=outR1; assign inS21=outR1; assign inA0=outACC; assign inS31=outACC; assign inACC=outA; assign inA1=outS2; assign inS30=outS2; assign inR1=outS1; assign inR0
11、=outS0;endmodule/加法器模塊module add(A,B,C); parameter WIDTH=8; input WIDTH-1:0 A, B; output WIDTH-1:0 C; wire WIDTH:0 DATA; assign DATA=A+B; assign C=DATA7:0;endmodule/寄存器模塊module register(D,Clk,reset,load,Q); parameter WIDTH=8; input WIDTH-1:0 D; input Clk,reset,load; output reg WIDTH-1:0 Q;always (po
12、sedge Clk)if (reset)beginQ = 8b0;end else if (load)beginQ b) out=1; else out=0; endendmodule/存儲(chǔ)器模塊module ROM(ROM_data, ROM_addr);parameter data_WIDTH=8;parameter addr_WIDTH=8;output addr_WIDTH-1:0 ROM_data;input addr_WIDTH-1:0 ROM_addr;reg addr_WIDTH-1:0 ROM data_WIDTH-1:0; / defining 4x2 ROMassign
13、ROM_data = ROMROM_addr; / reading ROM content at the address ROM_addrinitial $readmemb (ROM_data.txt, ROM, 0, 3); / load ROM content from ROM_data.txt fileendmodule/寄存器模塊module register(D,Clk,reset,load,Q); parameter WIDTH=8; input WIDTH-1:0 D; input Clk,reset,load; output reg WIDTH-1:0 Q;always (po
14、sedge Clk)if (reset)beginQ = 8b0;end else if (load)beginQ = D;endendmodule/加法器模塊module add(A,B,C); parameter WIDTH=8; input WIDTH-1:0 A, B; output WIDTH-1:0 C; wire WIDTH:0 DATA; assign DATA=A+B; assign C=DATA7:0;endmodule/二路選擇器模塊module mux(s,x,y,m); parameter WIDTH=8; input WIDTH-1:0 x,y; input s;
15、output WIDTH-1:0 m;assign m =(s?y:x);endmodule5.1_1module lab5_1_1(input clk, input reset, input ain, output reg yout, output reg 3:0 count); reg 1:0 state, nextstate; parameter S0=0, S1=1, S2=2, S3=3; always (posedge clk) / always block to update state if (reset) begin state = S0; count = 0; end el
16、se state = nextstate; always (state or ain) / always block to compute output begin yout = 0; case(state) S0: if(!ain) yout = 1; S1: yout = 0; S2: yout = 0; S3: if(ain) yout = 1; endcase end always (posedge clk) / always block to compute output begin if(ain) count = count + 1; end always (state or ai
17、n) / always block to compute nextstate begin case(state) S0: if(ain) nextstate = S1; else nextstate = S0; S1: if(ain) nextstate = S2; else nextstate = S1; S2: if(ain) nextstate = S3; else nextstate = S2; S3: if(ain) nextstate = S1; else nextstate = S3; endcase end endmodule仿真程序：module lab5_1_1_tb();
18、 reg clk,reset,ain; wire yout; wire 3:0 count; integer i; parameter TIME = 400; parameter DELAY = 5; lab5_1_1 DUT (.clk(clk), .ain(ain), .count(count), .reset(reset), .yout(yout); initial begin #TIME $finish; end initial begin clk = 0; for(i = 0; i (TIME/DELAY); i = i + 1) #DELAY clk = clk; end init
19、ial begin reset = 1; #(4*DELAY) reset = 0; #(34*DELAY) reset = 1; #(2*DELAY) reset = 0; end initial begin ain = 0; #(8*DELAY) ain = ain; #(4*DELAY) ain = ain; #(12*DELAY) ain = ain; #(8*DELAY) ain = ain; #(4*DELAY) ain = ain; #(6*DELAY) ain = ain; #(6*DELAY) ain = ain; endendmodule5.1_2module lab5_1
20、_2(input clk, input reset, input 1:0 x, output reg yout, output reg 2:0 nextstate); reg 2:0 state; parameter S0=0, S11=1, S21=2, S31=3, S12=4, S22=5, S32=6; always (posedge clk) / always block to update state if (reset) begin state = S0; nextstate = S0; yout = 0; end else state = nextstate; always (
21、state) / always block to compute output begin case(state) S0: yout = yout; S12: yout = 0; S22: yout = 1; S32: yout = yout; endcase end always (state or x) / always block to compute nextstate begin case(state) S0: if(x = 1) nextstate = S11; else if(x = 3) nextstate = S21; else if(x = 2) nextstate = S
22、31; S11: if(x = 0) nextstate = S12; else if(x = 1) nextstate = S11; else if(x = 3) nextstate = S21; else if(x = 2) nextstate = S31; S12: if(x = 1) nextstate = S11; else if(x = 3) nextstate = S21; else if(x = 2) nextstate = S31; S21: if(x = 0) nextstate = S22; else if(x = 1) nextstate = S11; else if(
23、x = 3) nextstate = S21; else if(x = 2) nextstate = S31; S22: if(x = 1) nextstate = S11; else if(x = 3) nextstate = S21; else if(x = 2) nextstate = S31; S31: if(x = 0) nextstate = S32; else if(x = 1) nextstate = S11; else if(x = 3) nextstate = S21; else if(x = 2) nextstate = S31; S32: if(x = 1) nexts
24、tate = S11; else if(x = 3) nextstate = S21; else if(x = 2) nextstate = S31; endcase endendmodule仿真程序：module lab5_1_2_tb(); reg clk,reset; reg 1:0 x; wire 2:0 nextstate; wire yout; integer i; parameter TIME = 200; parameter DELAY = 5; lab5_1_2 DUT (.clk(clk), .x(x), .reset(reset), .yout(yout), .nexts
25、tate(nextstate); initial begin #TIME $finish; end initial begin clk = 0; for(i = 0; i (TIME/DELAY); i = i + 1) #DELAY clk = clk; end initial begin reset = 1; #(4*DELAY) reset = 0; end initial begin x = 0; #(8*DELAY) x = 3; #(2*DELAY) x = 2; #(2*DELAY) x = 0; #(4*DELAY) x = 2; #(2*DELAY) x = 0; #(2*D
26、ELAY) x = 3; #(2*DELAY) x = 0; #(2*DELAY) x = 1; #(2*DELAY) x = 0; #(2*DELAY) x = 2; #(2*DELAY) x = 3; #(2*DELAY) x = 0; #(6*DELAY) x = 2; #(6*DELAY) x = 0; endendmodule5.1_3module lab5_1_3(input clk, input reset, input x, output reg 2:0 yout, output reg 2:0 nextstate); reg 2:0 state; parameter S0=0
27、, S1=1, S2=2, S3=3, S4=4, S5=5; always (posedge clk) / always block to update state if (reset) begin state = S0; nextstate = S0; end else state = nextstate; always (state or x) / always block to compute output begin case(state) S0: yout = 0; S1: yout = 1; S2: yout = 3; S3: yout = 5; S4: yout = 7; S5
28、: yout = 2; endcase end always (x or state) / always block to compute nextstate begin case(state) S0: if(x) nextstate = S1; else nextstate = S0; S1: if(x) nextstate = S2; else nextstate = S1; S2: if(x) nextstate = S3; else nextstate = S2; S3: if(x) nextstate = S4; else nextstate = S3; S4: if(x) next
29、state = S5; else nextstate = S4; S5: if(x) nextstate = S0; else nextstate = S5; endcase endendmodule仿真程序：module lab5_1_3_tb(); reg clk,reset; reg x; wire 2:0 nextstate; wire 2:0 yout; integer i; parameter TIME = 400; parameter DELAY = 5; lab5_1_3 DUT (.clk(clk), .x(x), .reset(reset), .yout(yout), .n
30、extstate(nextstate); initial begin #TIME $finish; end initial begin clk = 0; for(i = 0; i (TIME/DELAY); i = i + 1) #DELAY clk = clk; end initial begin reset = 1; #(4*DELAY) reset = 0; end initial begin x = 0; #(8*DELAY) x = 1; #(2*DELAY) x = 1; #(2*DELAY) x = 0; #(2*DELAY) x = 1; #(2*DELAY) x = 0; #
31、(2*DELAY) x = 1; #(2*DELAY) x = 0; #(2*DELAY) x = 1; #(2*DELAY) x = 0; #(2*DELAY) x = 1; #(2*DELAY) x = 1; #(2*DELAY) x = 0; #(2*DELAY) x = 1; #(2*DELAY) x = 0; #(2*DELAY) x = 1; #(2*DELAY) x = 0; #(2*DELAY) x = 1; #(2*DELAY) x = 0; endendmodule5.2module lab5_2_1(input clk, input reset, input ain, o
32、utput reg yout, output reg 3:0 count); reg 1:0 state, nextstate; parameter S0=0, S1=1, S2=2, S3=3; always (posedge clk) / always block to update state if (reset) begin state = S0; count = 0; end else begin state = nextstate; if(ain) count = count + 1; end always (state) / always block to compute out
33、put begin yout = 0; case(state) S0: yout = 0; S1: yout = 0; S2: yout = 0; S3: yout = 1; endcase end always (posedge clk) / always block to compute output begin end always (state or ain) / always block to compute nextstate begin case(state) S0: if(ain) nextstate = S1; else nextstate = S0; S1: if(ain)
34、 nextstate = S2; else nextstate = S1; S2: if(ain) nextstate = S3; else nextstate = S2; S3: if(ain) nextstate = S1; else nextstate = S3; endcase end endmodule仿真程序:module lab5_2_1_tb(); reg clk,reset,ain; wire yout; wire 3:0 count; integer i; parameter TIME = 400; parameter DELAY = 5; lab5_2_1 DUT (.c
35、lk(clk), .ain(ain), .count(count), .reset(reset), .yout(yout); initial begin #TIME $finish; end initial begin clk = 0; for(i = 0; i (TIME/DELAY); i = i + 1) #DELAY clk = clk; end initial begin reset = 1; #(4*DELAY) reset = 0; #(34*DELAY) reset = 1; #(2*DELAY) reset = 0; end initial begin ain = 0; #(
36、8*DELAY) ain = ain; #(4*DELAY) ain = ain; #(12*DELAY) ain = ain; #(8*DELAY) ain = ain; #(4*DELAY) ain = ain; #(6*DELAY) ain = ain; #(6*DELAY) ain = ain; endendmodul指導(dǎo)教師評(píng)定意見(jiàn)一、原創(chuàng)性聲明 本人鄭重聲明本報(bào)告內(nèi)容，是由作者本人獨(dú)立完成的。有關(guān)觀點(diǎn)、方法、數(shù)據(jù)和文獻(xiàn)等的引用已在文中指出。除文中已注明引用的內(nèi)容外，本報(bào)告不包含任何其他個(gè)人或集體已經(jīng)公開(kāi)發(fā)表的作品成果，不存在剽竊、抄襲行為。 特此聲明！作者簽字: 二、對(duì)實(shí)驗(yàn)的學(xué)術(shù)評(píng)語(yǔ) 三、對(duì)實(shí)驗(yàn)的評(píng)分評(píng)分項(xiàng)目（分值）報(bào)告撰寫(xiě)（30分）實(shí)驗(yàn)過(guò)程（70分）最終評(píng)定（100分）得分 指導(dǎo)教師簽字: 年 月 日
華中科技大學(xué)Verilog語(yǔ)言實(shí)驗(yàn)報(bào)告.docx
