基于FPGA的CRC編解碼器設(shè)計(jì)說(shuō)明書
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Introduced FPGA
Programmable logic devices is a universal logic chip can be configured for various purposes, which is to achieve ASIC (Application Specific Integrated Circuit) semi-customized device, its emergence and development make electronic systems designers can use CAD tools to design their own ASIC device in the laboratory. Especially the emergence and development of FPGA (Field Programmable Gate Array), as a microprocessor, memory, the figures for electronic system design and set a new industry standard (You can purchase the standard product catalog in the sales market). Digital systems are facing to the developing of microprocessor, memory, FPGA those three standard building blocks constituting or their integration direction.
Using FPGA devices design digital circuit, can not only simplify the design process and can reduce the size and cost of the entire system, increasing system reliability. They do not need to spend the traditional sense a lot of time and effort required to create integrated circuits, to avoid the investment risk and become the fastest-growing industries of electronic devices group. The main advantage of using FPGA devices circuit design of digital systems is as follows:
(1) Design flexible
Using FPGA devices may not be limited to standard series device at logic functional . And logic can be modified at any stage of the system design and the use of the process, and only re-programming the using FPGA device can be completed, provides the system design for great flexibility.
(2) Increased functional density
Functional density means the number of logic functions can be integrated in given space. The count of components gate in programmable logic chip is high, a piece of FPGA can replace several films, dozens of films or even hundreds of small-scale digital integrated circuit chip. FPGA devices use fewer chips when achieves digital system, thus reducing the number of chips, reducing printed circuit board area and the number of printed circuit boards, eventually causing an overall reduction in system size.
(3) Improve reliability
Reducing the number of chips and the printed board, not only can reduce system size, but it greatly enhanced system reliability. System with a high degree of integration have much higher reliability than the same system with a low degree of integration designed by many standard components. Using FPGA device reduces the number of chips required to achieve the system, the number of leads and pads on the printed circuit board is also reduced, so the reliability of the system can be improved.
(4) Shortening the design cycle
Because of programmability and flexibility of FPGA devices, and use it to design a system, the time required is much shorter than the traditional method. FPGA devices have high integration, the printed circuit board layout simply when using. Meanwhile, after the success of the prototype design, due to the advanced development tools, high degree of automation, its logic is very simple and quick to modify. Therefore, using FPGA devices can greatly shorten the design cycle and accelerate speed to market, improve product competitiveness.
(5) Work fast
FPGA/CPLD devices work fast, generally can reach several hundred Hertz, far faster than the DSP device. And circuit series required to achieve the system is less after using FPGA devices, thus the working speed of the entire system will be improved.
(6) Increased system security performance
Many FPGA devices have encryption capabilities, using FPGA devices widely in system can effectively prevent the product from being illegally imitation of others.
(7) Reduce costs
Using FPGA devices to achieve digital system design, if only consider the price of the device itself, sometimes do not see its advantage, but the factors that affect the cost of the system is multifaceted. comprehensive consideration, cost advantages of using FPGA is obvious. First, using FPGA devices is easy to modify design, shorten the design cycle, allowing the system to reduce the cost of research and development; secondly, FPGA devices enable to reduce the printed circuit board area and the number of plug-ins required, thereby reducing the manufacturing cost of the system; once again, the use of FPGA devices enables the system to improve reliability, reduce maintenance workload, thereby reducing the cost of servicing the system. In short, the system design using FPGA devices cost savings.
FPGA design principles :
One important guiding principle of FPGA design: the balance and interchangeable of size and speed, this principle is reflected with a large number of validation in filter design behind.
Here, "area" means the number of FPGA / CPLD logic resources consumed by design , the FPGA can be measured by the consuming of flip-flop (FF) and a lookup table (LUT) , a more general approach can measure by the number of equivalent logic gates which occupied by design. "Speed" refers to the highest frequency can be achieved with stable operation on the chip, this frequency is determined by the design of the timing condition, and closely related to the clock cycle, PAD to PAD Time, Clock Setup Time, Clock Hold Time, Clock-to-Output Delay timing and many timing feature quantity. Area and speed are always imbued with FPGA design ,are the ultimate standard of design quality evaluation. Two basic concepts of area and speed: the balance of the area and the speed , the area and the speed of exchange.
Size and speed are a pair of opposites contradiction. Requires a design along with the smallest design area, and the highest operating frequency is unrealistic. A more scientific design goal should be under the premise of meeting the design timing requirements (including the requirements of the design frequency), occupying the smallest chip area. Or in the specified area, designed to make more timing margin, running higher frequency. Both targets fully reflects the thinking of the balance of the area and speed. About the area and speed requirements, should not be simply interpreted as the pursue of raising the engineers level and design perfection, but should recognize that they are directly related to quality and cost of the products . If the timing margin of the design is relatively large, run a relatively high frequency, which means design is more robust, the quality of the whole system is more certified; On the other hand, design consumes less area, it means that the unit chip can achieve more functional modules, needs less chips, the cost of the entire system also will be slashed. As two parts of the contradiction, area and speeds’ status are not the same. In contrast, to meet requirements of timing and operating frequency is more important, when the two conflict, using the criteria of speed priority.
Area and speed of exchange is an important idea in FPGA design. In theory, if a design have larger timing margin, and can run much higher frequency than design requirements, it will be able to reuse the function module to reduce the chip area consumed by entire design, this is the savings using the advantages of the speed to change area; On the contrary, if a design's timing requirements are high, conventional methods can not reach the design frequency, then generally make data flow serial-parallel transforming, parallel copy multiple operating modules, take on the "serial-parallel conversion" thought to operate on the entire design, conduct the "serial-parallel conversion"in date at the output of the chip module, from a macro point of view, the entire chip have meet the requirements of processing speed, this corresponds with the area replication and faster of exchange.
Give an example. Assuming input data stream of the digital signal processing system is 350Mb / s, while the processing speed in the FPGA design data processing module up to 150Mb / s, since the data throughput of processing module can not meet the requirements, direct implementation at FPGA is impossible. In this case, we should use"area-for-speed" thought, at least copied into three processing module, the input data first conduct serial-parallel conversion, then using these three modules conduct parallel processing, then the processing result conduct "serial conversion " to complete the data rate requirements. We look at both ends of the entire processing module, the data rate is 350Mb / s, while inside the FPGA, the data rate of each sub-module process is 150Mb / s, in fact, the indemnification of the entire data throughput is dependent on the three sub-modules parallel processing, that takes more advantage of the chip area, to achieve high-speed processing,to achieve the design through the "copy area in exchange for improving processing speed"thinking.
FPGA is the abbreviation of the field programmable gate array, it is the product on the basis of PAL, GAL, EPLD and other programmable devices' further development. It is appeared as a semi-custom circuit in ASIC field, it not only solve the lack of custom circuits, but also overcome the defect of limited numbers of gates in original programmable device.
FPGA uses LCA (Logic Cell Array) such a new concept, including internal CLB (Configurable Logic Block), IOB (Input Output Block), and internal connections in three parts. The basic characteristics of FPGA:
(1) Using FPGA to design ASIC circuits, users do not need to cast film production can get applicative chips.
(2) FPGA can make the specimen of other full-custom or semi-custom ASIC circuits .
(3) FPGA internal have rich triggers and I / O pins.
(4) FPGA is one of the shortest design cycle, the lowest development costs, the least risky devices in ASIC circuits.
(5)FPGA uses high-speed CHMOS technology with low power, can be compatible with CMOS, TTL level.
It can be said that the FPGA chip is one of the best choice for small-scale systems to improve system integration and reliability .
Currently, FPGA have many varieties, XILINX's XC Series, TI company's TPC series, company's ALTERA series.
FPGA sets its work status by a program stored in the on-chip RAM, so when work, it needs to program the on-chip RAM. The user can use different programming form depending on the configuration mode.
When powered up, FPGA chip will read the data inside EPROM to the on-chip programming RAM. When the configuration is completed, FPGA go into working condition. After brownout, FPGA restore to the blank chip, the internal logic disappears, therefore, FPGA can be used repeatedly. FPGA programming don't need a dedicated FPGA programmer, just use common EPROM、PROM programmer. When the FPGA function need modified, just to change an piece of EPROM. Thus, one same FPGA, different programming data, can bring different circuit functions. Therefore, FPGA is very flexible.
There are a variety of FPGA configuration modes: parallel host mode for an FPGA plus an EPROM; master-slave mode can support a PROM programs multi-chip FPGA; serial mode can use serial PROM programs FPGA; peripheral mode can make FPGA to be used as peripherals of micro-processor, programmed by the microprocessor.
Verilog HDL is a hardware description language, used as multiple abstract design levels of digital system modeling from algorithm-level, gate-level to switch level. Digital systems can describe hierarchically, and can conduct timing modeling in the same description explicitly.
Verilog HDL language has the following ability to describe: behavioral characteristics of the design, the data flow characteristics of the design, structure and composition of the design as well as including response monitoring, response delay and waveform generation mechanism of design verification. All these use the same modeling language. In addition, Verilog HDL language provides programming language interface, through the interface, it can access design from external design in the simulation, verification period, including the simulation of specific control and operation.
Verilog HDL language not only defines the syntax but also defines a clear simulation and simulation semantics for grammatical structure. Thus, the model written by this language can use the Verilog emulator to verify. Language inherit multiple operator structure from C programming language. Verilog HDL provides expanded modeling capabilities, which many extensions initially difficult to understand.
FPGA介紹：
可編程邏輯器件是一種可以構(gòu)成各種用途邏輯的通用芯片，它是實(shí)現(xiàn)專用集成電路ASIC（Application Specific Integrated Circuit）的半定制器件，它的出現(xiàn)和發(fā)展使電子系統(tǒng)設(shè)計(jì)師借助于CAD手段在實(shí)驗(yàn)室里就可以設(shè)計(jì)自己的ASIC器件。特別是FPGA（Field Programmable Gate Array）的產(chǎn)生與發(fā)展，使其成為繼微處理器、存儲(chǔ)器之后的為電子數(shù)字系統(tǒng)設(shè)計(jì)而確定的又一種新的工業(yè)標(biāo)準(zhǔn)(即可以按標(biāo)準(zhǔn)產(chǎn)品目錄在銷售市場(chǎng)上購(gòu)到)。數(shù)字系統(tǒng)正朝向以微處理器、存儲(chǔ)器、FPGA三種標(biāo)準(zhǔn)積木塊構(gòu)成或是它們的集成方向發(fā)展。
使用FPGA器件設(shè)計(jì)數(shù)字電路，不僅可以簡(jiǎn)化設(shè)計(jì)過(guò)程，而且可以降低整個(gè)系統(tǒng)的體積和成本，增加系統(tǒng)的可靠性。它們無(wú)需花費(fèi)傳統(tǒng)意義下制造集成電路所需大量時(shí)間和精力，避免了投資風(fēng)險(xiǎn)，成為電子器件行業(yè)中發(fā)展最快的一族。使用FPGA器件設(shè)計(jì)數(shù)字系統(tǒng)電路的主要優(yōu)點(diǎn)如下：
（1）設(shè)計(jì)靈活
使用FPGA器件，可不受標(biāo)準(zhǔn)系列器件在邏輯功能上的限制。而且修改邏輯可在系統(tǒng)設(shè)計(jì)和使用過(guò)程的任一階段中進(jìn)行，并且只須對(duì)所用的FPGA器件進(jìn)行重新編程即可完成，給系統(tǒng)設(shè)計(jì)提供了很大的靈活性。
（2）增大功能密集度
功能密集度是指在給定的空間能集成的邏輯功能數(shù)量。可編程邏輯芯片內(nèi)的組件門數(shù)高，一片F(xiàn)PGA可代替幾片、幾十片乃至上百片中小規(guī)模的數(shù)字集成電路芯片。FPGA器件實(shí)現(xiàn)數(shù)字系統(tǒng)時(shí)用的芯片數(shù)量少，從而減少芯片的數(shù)目，減少印刷線路板面積和印刷線路板數(shù)目，最終導(dǎo)致系統(tǒng)規(guī)模的全面縮減。
（3）提高可靠性
減少芯片和印刷板數(shù)目，不僅能縮小系統(tǒng)規(guī)模，而且它還極大的提高了系統(tǒng)的可靠性。具有較高集成度的系統(tǒng)比用許多低集成度的標(biāo)準(zhǔn)組件設(shè)計(jì)的相同系統(tǒng)具有高得多的可靠性。使用FPGA器件減少了實(shí)現(xiàn)系統(tǒng)所需要的芯片數(shù)目，在印刷線路板上的引線以及焊點(diǎn)數(shù)量也減少了，所以系統(tǒng)的可靠性得以提高。
（4）縮短設(shè)計(jì)周期
由于FPGA器件的可編程性和靈活性，用它來(lái)設(shè)計(jì)一個(gè)系統(tǒng)所需時(shí)間比傳統(tǒng)方法大為縮短。FPGA器件集成度高，使用時(shí)印刷線路板電路布局布線簡(jiǎn)單。同時(shí)，在樣機(jī)設(shè)計(jì)成功后，由于開發(fā)工具先進(jìn)，自動(dòng)化程度高，對(duì)其進(jìn)行邏輯修改也十分簡(jiǎn)便迅速。因此，使用FPGA器件可大大縮短系統(tǒng)的設(shè)計(jì)周期，加快產(chǎn)品投放市場(chǎng)的速度，提高產(chǎn)品的競(jìng)爭(zhēng)能力。
（5）工作速度快
FPGA/CPLD器件的工作速度快，一般可以達(dá)到幾百兆赫茲，遠(yuǎn)遠(yuǎn)大于DSP器件。并且使用FPGA器件后實(shí)現(xiàn)系統(tǒng)所需要的電路級(jí)數(shù)又少，因而整個(gè)系統(tǒng)的工作速度會(huì)得到提高。
（6）增加系統(tǒng)的保密性能
很多FPGA器件都具有加密功能，在系統(tǒng)中廣泛的使用FPGA器件可以有效防止產(chǎn)品被他人非法仿制。
（7）降低成本
使用FPGA器件實(shí)現(xiàn)數(shù)字系統(tǒng)設(shè)計(jì)時(shí)，如果僅從器件本身的價(jià)格考慮，有時(shí)還看不出來(lái)它的優(yōu)勢(shì)，但是影響系統(tǒng)成本的因素是多方面的，綜合考慮，使用FPGA的成本優(yōu)越性是很明顯的。首先，使用FPGA器件修改設(shè)計(jì)方便，設(shè)計(jì)周期縮短，使系統(tǒng)的研制開發(fā)費(fèi)用降低；其次，F(xiàn)PGA器件可使印刷線路板面積和需要的插件減少，從而使系統(tǒng)的制造費(fèi)用降低；再次，使用FPGA器件能使系統(tǒng)的可靠性提高，維修工作量減少，進(jìn)而使系統(tǒng)的維修服務(wù)費(fèi)用降低?？傊褂肍PGA器件進(jìn)行系統(tǒng)設(shè)計(jì)能節(jié)約成本。
FPGA設(shè)計(jì)原則：
FPGA設(shè)計(jì)的一個(gè)重要指導(dǎo)原則：面積和速度的平衡與互換，這個(gè)原則在后邊的濾波器設(shè)計(jì)中有大量的驗(yàn)證體現(xiàn)。
這里“面積”指一個(gè)設(shè)計(jì)消耗FPGA/CPLD的邏輯資源的數(shù)量，對(duì)于FPGA可以用所消耗的觸發(fā)器(FF)和查找表(LUT)來(lái)衡量，更一般的方法可以用設(shè)計(jì)所占用的等價(jià)邏輯門數(shù)來(lái)衡量?！八俣取敝冈谛酒戏€(wěn)定運(yùn)行所能夠達(dá)到的最高頻率，這個(gè)頻率由設(shè)計(jì)的時(shí)序狀況決定，和時(shí)鐘周期，PADto PAD Time, Clock Setup Time, Clock Hold Time, Clock-to-Output Delay等眾多時(shí)序特征量密切相關(guān)。面積和速度貫穿著FPGA設(shè)計(jì)的始終，是設(shè)計(jì)質(zhì)量評(píng)價(jià)的終極標(biāo)準(zhǔn)。關(guān)于面積和速度的兩個(gè)最基本的概念：面積與速度的平衡和面積與速度的互換。
面積和速度是一對(duì)對(duì)立統(tǒng)一的矛盾體。要求一個(gè)設(shè)計(jì)同時(shí)具備設(shè)計(jì)面積最小，運(yùn)行頻率最高是不現(xiàn)實(shí)的。更科學(xué)的設(shè)計(jì)目標(biāo)應(yīng)該是在滿足設(shè)計(jì)時(shí)序要求(包含對(duì)設(shè)計(jì)頻率的要求)的前提下，占用最小的芯片面積?；蛘咴谒?guī)定的面積下，使設(shè)計(jì)的時(shí)序余量更大，頻率跑得更高。這兩種目標(biāo)充分體現(xiàn)了面積和速度的平衡的思想。關(guān)于面積和速度的要求，不應(yīng)該簡(jiǎn)單地理解為工程師水平的提高和設(shè)計(jì)完美性的追求，而應(yīng)該認(rèn)識(shí)到它們是和產(chǎn)品的質(zhì)量和成本直接相關(guān)的。如果設(shè)計(jì)的時(shí)序余量比較大，跑的頻率比較高，意味著設(shè)計(jì)更加健壯，整個(gè)系統(tǒng)的質(zhì)量更有保證；另一方面，設(shè)計(jì)所消耗的面積更小，則意味著單位芯片能實(shí)現(xiàn)更多的功能模塊，需要的芯片數(shù)量更少，整個(gè)系統(tǒng)的成本也大幅度削減。作為矛盾的兩個(gè)組成部分，面積和速度的地位是不一樣的。相比之下，滿足時(shí)序、工作頻率的要求更重要一些，當(dāng)兩者沖突時(shí)，采用速度優(yōu)先的準(zhǔn)則。
面積和速度的互換是 FPGA設(shè)計(jì)的一個(gè)重要思想。從理論上講，一個(gè)設(shè)計(jì)如果時(shí)序余量較大，所能跑的頻率遠(yuǎn)遠(yuǎn)高于設(shè)計(jì)要求，那么就能通過(guò)功能模塊復(fù)用減少整個(gè)設(shè)計(jì)消耗的芯片面積，這就是用速度的優(yōu)勢(shì)換面積的節(jié)約；反之，如果一個(gè)設(shè)計(jì)的時(shí)序要求很高，普通方法達(dá)不到設(shè)計(jì)頻率，那么一般可以通過(guò)將數(shù)據(jù)流串并轉(zhuǎn)換，并行復(fù)制多個(gè)操作模塊，對(duì)整個(gè)設(shè)計(jì)采取“串并轉(zhuǎn)換”的思想進(jìn)行運(yùn)作，在芯片輸出模塊再在對(duì)數(shù)據(jù)進(jìn)行“并串轉(zhuǎn)換”，從宏觀上看整個(gè)芯片滿足了處理速度的要求，這相當(dāng)于用面積復(fù)制換速度提高。
舉一個(gè)例子。假設(shè)數(shù)字信號(hào)處理系統(tǒng)輸入數(shù)據(jù)流的速率是350Mb/s，而在FPGA上設(shè)計(jì)的數(shù)據(jù)處理模塊的處理速度最大為150Mb/s，由于處理模塊的數(shù)據(jù)吞吐量滿足不了要求，直接在FPGA上實(shí)現(xiàn)是不可能的。這種情況下，就應(yīng)該利用“面積換速度”的思想，至少?gòu)?fù)制成3個(gè)處理模塊，首先將輸入數(shù)據(jù)進(jìn)行串并轉(zhuǎn)換，然后利用這三個(gè)模塊并行處理分配的數(shù)據(jù)，然后將處理結(jié)果“并串變換”，就完成數(shù)據(jù)速率的要求。我們?cè)谡麄€(gè)處理模塊的兩端看，數(shù)據(jù)速率是350Mb/s，而在FPGA的內(nèi)部看，每個(gè)子模塊處理的數(shù)據(jù)速率是150Mb/s，其實(shí)整個(gè)數(shù)據(jù)的吞吐量的保障是依賴于3個(gè)子模塊并行處理完成的，也就是說(shuō)利用了占用更多的芯片面積，實(shí)現(xiàn)了高速處理，通過(guò)“面積的復(fù)制換取處理速度的提高”的思想實(shí)現(xiàn)了設(shè)計(jì)。
FPGA是英文Field Programmable Gate Array的縮寫，即現(xiàn)場(chǎng)可編程門陣列，它是在PAL、GAL、EPLD等可編程器件的基礎(chǔ)上進(jìn)一步發(fā)展的產(chǎn)物。它是作為專用集成電路（ASIC）領(lǐng)域中的一種半定制電路而出現(xiàn)的，既解決了定制電路的不足，又克服了原有可編程器件中門電路數(shù)有限的缺點(diǎn)。
FPGA采用了邏輯單元陣列LCA（Logic Cell Array）這樣一個(gè)新概念，內(nèi)部包括可配置邏輯模塊CLB（Configurable Logic Block）、輸出輸入模塊IOB（Input Output Block）和內(nèi)部連線（Interconnect）三個(gè)部分。
FPGA的基本特點(diǎn)：
1）采用FPGA設(shè)計(jì)ASIC電路，用戶不需要投片生產(chǎn)，就能得到合用的芯片。
2）FPGA可做其它全定制或半定制ASIC電路的中試樣片。
3）FPGA內(nèi)部有豐富的觸發(fā)器和I／O引腳。
4）FPGA是ASIC電路中設(shè)計(jì)周期最短、開發(fā)費(fèi)用最低、風(fēng)險(xiǎn)最小的器件之一。
5）FPGA采用高速CHMOS工藝，功耗低，可以與CMOS、TTL電平兼容。
可以說(shuō)，F(xiàn)PGA芯片是小批量系統(tǒng)提高系統(tǒng)集成度、可靠性的最佳選擇之一。
目前FPGA的品種很多，有XILINX的XC系列、TI公司的TPC系列、ALTERA公司的FIEX系列等。?
FPGA是由存放在片內(nèi)RAM中的程序來(lái)設(shè)置其工作狀態(tài)的，因此，工作時(shí)需要對(duì)片內(nèi)的RAM進(jìn)行編程。用戶可以根據(jù)不同的配置模式，采用不同的編程方式。
加電時(shí)，F(xiàn)PGA芯片將EPROM中數(shù)據(jù)讀入片內(nèi)編程RAM中，配置完成后，F(xiàn)PGA進(jìn)入工作狀態(tài)。掉電后，F(xiàn)PGA恢復(fù)成白片，內(nèi)部邏輯關(guān)系消失，因此，F(xiàn)PGA能夠反復(fù)使用。FPGA的編程無(wú)須專用的FPGA編程器，只須用通用的EPROM、PROM編程器即可。當(dāng)需要修改FPGA功能時(shí)，只需換一片EPROM即可。這樣，同一片F(xiàn)PGA，不同的編程數(shù)據(jù)，可以產(chǎn)生不同的電路功能。因此，F(xiàn)PGA非常靈活。
FPGA有多種配置模式：并行主模式為一片F(xiàn)PGA加一片EPROM的方式；主從模式可以支持一片PROM編程多片F(xiàn)PGA；串行模式可以采用串行PROM編程FPGA；外設(shè)模式可以將FPGA作為微處理器的外設(shè)，由微處理器對(duì)其編程。
Verilog HDL是一種硬件描述語(yǔ)言，用于從算法級(jí)、門級(jí)到開關(guān)級(jí)的多種抽象設(shè)計(jì)層次的數(shù)字系統(tǒng)建模。數(shù)字系統(tǒng)能夠按層次描述，并可在相同描述中顯式地進(jìn)行時(shí)序建模。
Verilog HDL 語(yǔ)言具有下述描述能力：設(shè)計(jì)的行為特性、設(shè)計(jì)的數(shù)據(jù)流特性、設(shè)計(jì)的結(jié)構(gòu)組成以及包含響應(yīng)監(jiān)控和設(shè)計(jì)驗(yàn)證方面的時(shí)延和波形產(chǎn)生機(jī)制。所有這些都使用同一種建模語(yǔ)言。此外，Verilog HDL語(yǔ)言提供了編程語(yǔ)言接口，通過(guò)該接口可以在模擬、驗(yàn)證期間從設(shè)計(jì)外部訪問(wèn)設(shè)計(jì)，包括模擬的具體控制和運(yùn)行。
Verilog HDL語(yǔ)言不僅定義了語(yǔ)法，而且對(duì)每個(gè)語(yǔ)法結(jié)構(gòu)都定義了清晰的模擬、仿真語(yǔ)義。因此，用這種語(yǔ)言編寫的模型能夠使用Verilog仿真器進(jìn)行驗(yàn)證。語(yǔ)言從C編程語(yǔ)言中繼承了多種操作符和結(jié)構(gòu)。Verilog HDL提供了擴(kuò)展的建模能力，其中許多擴(kuò)展最初很難理解。
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