基于FPGA的HDB3編解碼器的設(shè)計說明書

基于FPGA的HDB3編解碼器的設(shè)計說明書,基于,fpga,hdb3,編解碼器,設(shè)計,說明書,仿單 附錄1：基于VHDL語言的HDB3編解碼器源程序 附錄1.1 HDB3編碼器源程序 －－－－－－輸出相對于輸入延時了五個脈沖周期 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hdb3_coding is port( data_in :in std_logic; clock :in std_logic; data_out :out std_logic_vector(1 downto 0)); end hdb3_coding; architecture rtl of hdb3_coding is signal reg :std_logic_vector(3 downto 0); signal parity :std_logic; －－記錄破壞點間1碼個數(shù)的奇偶性 signal judge_v :std_logic; －－判斷是否有破壞符 signal grant_cnt:std_logic; －－允許開始計算破壞點間的1碼個數(shù) signal last_sign:std_logic; －－上一輸出的符號 signal v_cnt :std_logic_vector(2 downto 0);－－v點位置跟蹤計數(shù)器 begin process(clock) －－ 移位寄存器，插V begin if rising_edge(clock) then if data_in='0' and reg(3 downto 1)=“000“ then reg<=('1' & reg(3 downto 1)); judge_v<='1'; grant_cnt<='1'; else reg<=data_in & reg(3 downto 1); judge_v<='0'; grant_cnt<='0'; end if; end if; end process; process(clock) －－計數(shù) begin if rising_edge(clock) then if grant_cnt='1' and data_in='0' then parity<='0'; elsif grant_cnt='1' and data_in='1' then parity<='1'; elsif data_in='1' then parity<=not parity; end if; end if; end process; process(clock) －－V點跟蹤 begin if rising_edge(clock) then if judge_v='1' then v_cnt<=“000“; elsif v_cnt=“111“ then v_cnt<=v_cnt; else v_cnt<=v_cnt+1; end if; end if; end process; process(clock) －－編碼輸出 begin if rising_edge(clock) then if reg(0)='1' then if v_cnt<=“010“ then if last_sign='1' then data_out<=“11“; else data_out<=“01“; end if; elsif last_sign='1' then data_out<=“01“;last_sign<=not last_sign; elsif last_sign='0' then data_out<=“11“;last_sign<=not last_sign; end if; elsif judge_v='1' and parity='0' then if last_sign='1' then data_out<=“01“;last_sign<=not last_sign; else data_out<=“11“;last_sign<=not last_sign; end if; else data_out<=“00“; end if; end if; end process; end rtl; 附錄1.2 HDB3解碼器源程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hdb3_decode is port(data1 :in std_logic; －－高位 data0 :in std_logic; －－低位 clock :in std_logic; data_out :out std_logic); end hdb3_decode; architecture rtl of hdb3_decode is signal reg0 :std_logic_vector(4 downto 0); signal reg1 :std_logic_vector(4 downto 0); begin process(clock) begin if rising_edge(clock) then if data0='1' and data1='0' and reg0(4 downto 1)=“0001“ and reg1(4 downto 1)=“0000“ then reg0<=“00001“;reg1<=“00000“; elsif data0='1' and data1='1' and reg0(4 downto 1)=“0001“ and reg1(4 downto 1)=“0001“ then reg0<=“00001“;reg1<=“00000“; elsif data0='1' and data1='1' and reg0(4 downto 2)=“001“ and reg1(4 downto 2)=“001“ then reg0<=“0000“ & reg0(1);reg1<=“0000“ & reg1(1); elsif data0='1' and data1='0' and reg0(4 downto 2)=“001“ and reg1(4 downto 2)=“000“ then reg0<=“0000“ & reg0(1);reg1<=“0000“ & reg1(1); else reg0<=data0 & reg0(4 downto 1);reg1<=data1 & reg1(4 downto 1); end if; end if; end process; process(clock) begin if rising_edge(clock) then if reg0(0)='1' or reg1(0)='1' then data_out<='1'; else data_out<='0'; end if; end if; end process; end rtl;