DZ214單片機(jī)控制制冷機(jī)來達(dá)到控制溫度

DZ214單片機(jī)控制制冷機(jī)來達(dá)到控制溫度,DZ214,單片機(jī),控制,制冷機(jī),達(dá)到,溫度 1FeaturesCompatible with MCS-51 Products4K Bytes of In-System Programmable (ISP) Flash Memory Endurance: 1000 Write/Erase Cycles4.0V to 5.5V Operating RangeFully Static Operation: 0 Hz to 33 MHzThree-level Program Memory Lock128 x 8-bit Internal RAM32 Programmable I/O LinesTwo 16-bit Timer/CountersSix Interrupt SourcesFull Duplex UART Serial ChannelLow-power Idle and Power-down ModesInterrupt Recovery from Power-down ModeWatchdog TimerDual Data PointerPower-off FlagFast Programming TimeFlexible ISP Programming (Byte and Page Mode)DescriptionThe AT89S51 is a low-power, high-performance CMOS 8-bit microcontroller with 4Kbytes of in-system programmable Flash memory. The device is manufactured usingAtmels high-density nonvolatile memory technology and is compatible with the indus-try-standard 80C51 instruction set and pinout. The on-chip Flash allows the programmemory to be reprogrammed in-system or by a conventional nonvolatile memory pro-grammer. By combining a versatile 8-bit CPU with in-system programmable Flash on amonolithic chip, the Atmel AT89S51 is a powerful microcontroller which provides ahighly-flexible and cost-effective solution to many embedded control applications.The AT89S51 provides the following standard features: 4K bytes of Flash, 128 bytes ofRAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator, andclock circuitry. In addition, the AT89S51 is designed with static logic for operationdown to zero frequency and supports two software selectable power saving modes.The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, andinterrupt system to continue functioning. The Power-down mode saves the RAM con-tents but freezes the oscillator, disabling all other chip functions until the next externalinterrupt or hardware reset.8-bit Microcontroller with 4K Bytes In-System Programmable FlashAT89S51Rev. 2487A10/012 AT89S512487A10/01Pin ConfigurationsPDIPTQFP12345678910111213141516171819204039383736353433323130292827262524232221 P1.0 P1.1P1.2P1.3P1.4(MOSI) P1.5(MISO) P1.6(SCK) P1.7RST(RXD) P3.0(TXD) P3.1(INT0) P3.2(INT1) P3.3(T0) P3.4(T1) P3.5(WR) P3.6(RD) P3.7XTAL2XTAL1GNDVCCP0.0 (AD0)P0.1 (AD1)P0.2 (AD2)P0.3 (AD3)P0.4 (AD4)P0.5 (AD5)P0.6 (AD6)P0.7 (AD7)EA/VPPALE/PROGPSENP2.7 (A15)P2.6 (A14)P2.5 (A13)P2.4 (A12)P2.3 (A11)P2.2 (A10)P2.1 (A9)P2.0 (A8)1234567891011333231302928272625242344434241403938373635341213141516171819202122(MOSI) P1.5(MISO) P1.6(SCK) P1.7RST(RXD) P3.0NC(TXD) P3.1(INT0) P3.2(INT1) P3.3(T0) P3.4(T1) P3.5P0.4 (AD4)P0.5 (AD5)P0.6 (AD6)P0.7 (AD7)EA/VPPNCALE/PROGPSENP2.7 (A15)P2.6 (A14)P2.5 (A13)P1.4P1.3P1.2P1.1 P1.0 NCVCCP0.0 (AD0)P0.1 (AD1)P0.2 (AD2)P0.3 (AD3)(WR) P3.6(RD) P3.7XTAL2XTAL1GNDGND(A8) P2.0(A9) P2.1(A10) P2.2(A11) P2.3(A12) P2.4PLCC78910111213141516173938373635343332313029(MOSI) P1.5(MISO) P1.6(SCK) P1.7RST(RXD) P3.0NC(TXD) P3.1(INT0) P3.2(INT1) P3.3(T0) P3.4(T1) P3.5P0.4 (AD4)P0.5 (AD5)P0.6 (AD6)P0.7 (AD7)EA/VPPNCALE/PROGPSENP2.7 (A15)P2.6 (A14)P2.5 (A13)65432144434241401819202122232425262728(WR) P3.6(RD) P3.7XTAL2XTAL1GNDNC(A8) P2.0(A9) P2.1(A10) P2.2(A11) P2.3(A12) P2.4P1.4 P1.3P1.2P1.1 P1.0 NCVCCP0.0 (AD0)P0.1 (AD1)P0.2 (AD2)P0.3 (AD3)3 AT89S512487A10/01Block DiagramPORT 2 DRIVERSPORT 2LATCHP2.0 - P2.7FLASHPORT 0LATCHRAMPROGRAMADDRESSREGISTERBUFFERPCINCREMENTERPROGRAMCOUNTERDUAL DPTRINSTRUCTIONREGISTERBREGISTERINTERRUPT, SERIAL PORT,AND TIMER BLOCKSSTACKPOINTERACCTMP2TMP1ALUPSWTIMINGANDCONTROLPORT 1 DRIVERSP1.0 - P1.7PORT 3LATCHPORT 3 DRIVERSP3.0 - P3.7OSCGNDVCCPSENALE/PROGEA / VPPRSTRAM ADDR.REGISTERPORT 0 DRIVERSP0.0 - P0.7PORT 1LATCHWATCHDOGISPPORTPROGRAMLOGIC4 AT89S512487A10/01Pin DescriptionVCCSupply voltage.GNDGround.Port 0Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eightTTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedanceinputs. Port 0 can also be configured to be the multiplexed low-order address/data bus duringaccesses to external program and data memory. In this mode, P0 has internal pull-ups.Port 0 also receives the code bytes during Flash programming and outputs the code bytesduring program verification. External pull-ups are required during program verification. Port 1Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers cansink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by theinternal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally beingpulled low will source current (IIL) because of the internal pull-ups. Port 1 also receives the low-order address bytes during Flash programming and verification.Port 2Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers cansink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by theinternal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally beingpulled low will source current (IIL) because of the internal pull-ups.Port 2 emits the high-order address byte during fetches from external program memory andduring accesses to external data memory that use 16-bit addresses (MOVX DPTR). In thisapplication, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to externaldata memory that use 8-bit addresses (MOVX RI), Port 2 emits the contents of the P2 Spe-cial Function Register.Port 2 also receives the high-order address bits and some control signals during Flash pro-gramming and verification.Port 3Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers cansink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by theinternal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally beingpulled low will source current (IIL) because of the pull-ups.Port 3 receives some control signals for Flash programming and verification.Port 3 also serves the functions of various special features of the AT89S51, as shown in thefollowing table.Port PinAlternate FunctionsP1.5MOSI (used for In-System Programming)P1.6MISO (used for In-System Programming)P1.7SCK (used for In-System Programming)5 AT89S512487A10/01 RSTReset input. A high on this pin for two machine cycles while the oscillator is running resets thedevice. This pin drives High for 98 oscillator periods after the Watchdog times out. The DIS-RTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default stateof bit DISRTO, the RESET HIGH out feature is enabled.ALE/PROGAddress Latch Enable (ALE) is an output pulse for latching the low byte of the address duringaccesses to external memory. This pin is also the program pulse input (PROG) during Flashprogramming. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and maybe used for external timing or clocking purposes. Note, however, that one ALE pulse isskipped during each access to external data memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulledhigh. Setting the ALE-disable bit has no effect if the microcontroller is in external executionmode.PSENProgram Store Enable (PSEN) is the read strobe to external program memory. When the AT89S51 is executing code from external program memory, PSEN is activatedtwice each machine cycle, except that two PSEN activations are skipped during each accessto external data memory. EA/VPPExternal Access Enable. EA must be strapped to GND in order to enable the device to fetchcode from external program memory locations starting at 0000H up to FFFFH. Note, however,that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flashprogramming.XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.XTAL2Output from the inverting oscillator amplifierPort PinAlternate FunctionsP3.0RXD (serial input port)P3.1TXD (serial output port)P3.2INT0 (external interrupt 0)P3.3INT1 (external interrupt 1)P3.4T0 (timer 0 external input)P3.5T1 (timer 1 external input)P3.6WR (external data memory write strobe)P3.7RD (external data memory read strobe)6 AT89S512487A10/01Special Function RegistersA map of the on-chip memory area called the Special Function Register (SFR) space is shownin Table 1.Note that not all of the addresses are occupied, and unoccupied addresses may not be imple-mented on the chip. Read accesses to these addresses will in general return random data,and write accesses will have an indeterminate effect.Table 1. AT89S51 SFR Map and Reset Values0F8H0FFH0F0HB000000000F7H0E8H0EFH0E0HACC000000000E7H0D8H0DFH0D0HPSW000000000D7H0C8H0CFH0C0H0C7H0B8HIPXX0000000BFH0B0HP3111111110B7H0A8HIE0X0000000AFH0A0HP211111111AUXR1XXXXXXX0WDTRSTXXXXXXXX0A7H98HSCON00000000SBUFXXXXXXXX9FH90HP11111111197H88HTCON00000000TMOD00000000TL000000000TL100000000TH000000000TH100000000AUXRXXX00XX08FH80HP011111111SP00000111DP0L00000000DP0H00000000DP1L00000000DP1H00000000PCON0XXX000087H7 AT89S512487A10/01User software should not write 1s to these unlisted locations, since they may be used in futureproducts to invoke new features. In that case, the reset or inactive values of the new bits willalways be 0.Interrupt Registers: The individual interrupt enable bits are in the IE register. Two prioritiescan be set for each of the five interrupt sources in the IP register.Dual Data Pointer Registers: To facilitate accessing both internal and external data memory,two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.The user should always initialize the DPS bit to the appropriate value before accessing therespective Data Pointer Register.Table 2. AUXR: Auxiliary RegisterAUXRAddress = 8EHReset Value = XXX00XX0BNot Bit AddressableWDIDLEDISRTODISALEBit76543210Reserved for future expansionDISALEDisable/Enable ALEDISALEOperating Mode0ALE is emitted at a constant rate of 1/6 the oscillator frequency1ALE is active only during a MOVX or MOVC instructionDISRTODisable/Enable Reset outDISRTO0Reset pin is driven High after WDT times out1Reset pin is input onlyWDIDLEDisable/Enable WDT in IDLE modeWDIDLE0WDT continues to count in IDLE mode1WDT halts counting in IDLE mode8 AT89S512487A10/01Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR.POF is set to “1” during power up. It can be set and rest under software control and is notaffected by reset.Memory OrganizationMCS-51 devices have a separate address space for Program and Data Memory. Up to 64Kbytes each of external Program and Data Memory can be addressed.Program MemoryIf the EA pin is connected to GND, all program fetches are directed to external memory.On the AT89S51, if EA is connected to VCC, program fetches to addresses 0000H throughFFFH are directed to internal memory and fetches to addresses 1000H through FFFFH aredirected to external memory.Data MemoryThe AT89S51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via directand indirect addressing modes. Stack operations are examples of indirect addressing, so the128 bytes of data RAM are available as stack space.Watchdog Timer (One-time Enabled with Reset-out)The WDT is intended as a recovery method in situations where the CPU may be subjected tosoftware upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, auser must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).When the WDT is enabled, it will increment every machine cycle while the oscillator is running.The WDT timeout period is dependent on the external clock frequency. There is no way to dis-able the WDT except through reset (either hardware reset or WDT overflow reset). WhenWDT overflows, it will drive an output RESET HIGH pulse at the RST pin.Using the WDTTo enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EHand 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will incrementevery machine cycle while the oscillator is running. This means the user must reset the WDTat least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1Hto WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written.When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESETpulse duration is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, itTable 3. AUXR1: Auxiliary Register 1AUXR1Address = A2HReset Value = XXXXXXX0BNot Bit AddressableDPSBit76543210 Reserved for future expansionDPSData Pointer Register SelectDPS0 Selects DPTR Registers DP0L, DP0H1 Selects DPTR Registers DP1L, DP1H9 AT89S512487A10/01should be serviced in those sections of code that will periodically be executed within the timerequired to prevent a WDT reset.WDT During Power-down and IdleIn Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are two methods of exitingPower-down mode: by a hardware reset or via a level-activated external interrupt, which isenabled prior to entering Power-down mode. When Power-down is exited with hardware reset,servicing the WDT should occur as it normally does whenever the AT89S51 is reset. ExitingPower-down with an interrupt is significantly different. The interrupt is held low long enough forthe oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To pre-vent the WDT from resetting the device while the interrupt pin is held low, the WDT is notstarted until the interrupt is pulled high. It is suggested that the WDT be reset during the inter-rupt service for the interrupt used to exit Power-down mode.To ensure that the WDT does not overflow within a few states of exiting Power-down, it is bestto reset the WDT just before entering Power-down mode.Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whetherthe WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit =0) as the default state. To prevent the WDT from resetting the AT89S51 while in IDLE mode,the user should always set up a timer that will periodically exit IDLE, service the WDT, andreenter IDLE mode.With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the countupon exit from IDLE.UARTThe UART in the AT89S51 operates the same way as the UART in the AT89C51. For furtherinformation on the UART operation, refer to the ATMEL Web site (http:/).From the home page, select Products, then 8051-Architecture Flash Microcontroller, thenProduct Overview. Timer 0 and 1Timer 0 and Timer 1 in the AT89S51 operate the same way as Timer 0 and Timer 1 in theAT89C51. For further information on the timers operation, refer to the ATMEL Web site(http:/). From the home page, select Products, then 8051-Architecture FlashMicrocontroller, then Product Overview. InterruptsThe AT89S51 has a total of five interrupt vectors: two external interrupts (INT0 and INT1), twotimer interrupts (Timers 0 and 1), and the serial port interrupt. These interrupts are all shown inFigure 1.Each of these interrupt sources can be individually enabled or disabled by setting or clearing abit in Special Function Register IE. IE also contains a global disable bit, EA, which disables allinterrupts at once.Note that Table 4 shows that bit position IE.6 is unimplemented. In the AT89S51, bit positionIE.5 is also unimplemented. User software should not write 1s to these bit positions, since theymay be used in future AT89 products.The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timersoverflow. The values are then polled by the circuitry in the next cycle10 AT89S512487A10/01. Figure 1. Interrupt SourcesTable 4. Interrupt Enable (IE) Register (MSB) (LSB)EAESET1EX1ET0EX0 Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables the interrupt.SymbolPositionFunctionEAIE.7Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.IE.6ReservedIE.5ReservedESIE.4Serial Port interrupt enable bitET1IE.3Timer 1 interrupt enable bitEX1IE.2External interrupt 1 enable bitET0IE.1Timer 0 interrupt enable bitEX0IE.0External interrupt 0 enable bitUser software should never write 1s to reserved bits, because they may be used in future AT89 products.IE1IE01100TF1TF0INT1INT0TIRI11 AT89S512487A10/01Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can beconfigured for use as an on-chip oscillator, as shown in Figure 2. Either a quartz crystal orceramic resonator may be used. To drive the device from an external clock source, XTAL2should be left unconnected while XTAL1 is driven, as shown in Figure 3. There are no require-ments on the duty cycle of the external clock signal, since the input to the internal clockingcircuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and lowtime specifications must be observed.Figure 2. Oscillator ConnectionsNote: C1, C2 = 30 pF 10 pF for Crystals = 40 pF 10 pF for Ceramic ResonatorsFigure 3. External Clock Drive ConfigurationIdle Mode In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. Themode is invoked by software. The content of the on-chip RAM and all the special functionregisters remain unchanged during this mode. The idle mode can be terminated by anyenabled interrupt or by a hardware reset. Note that when idle mode is terminated by a hardware reset, the device normally resumes pro-gram execution from where it left off, up to two machine cycles before the internal resetalgorithm takes control. On-chip hardware inhibits access to internal RAM in this event, butaccess to the port pins is not inhibited. To eliminate the possibility of an unexpected write to aport pin when idle mode is terminated by a reset, the instruction following the one that invokesidle mode should not write to a port pin or to external memory.Power-down Mode In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retaintheir values until the Power-down mode is terminated. Exit from Power-down mode can be ini-tiated either by a hardware reset or by activation of an enabled external interrupt into INT0 orINT1. Reset redefines the SFRs but does not change the on-chip RAM. The reset should notbe activated before VCC is restored to its normal operating level and must be held active longenough to allow the oscillator to restart and stabilize.C2XTAL2GNDXTAL1C1XTAL2XTAL1GNDNCEXTERNALOSCILLATORSIGNAL12 AT89S512487A10/01 Program Memory Lock BitsThe AT89S51 has three lock bits that can be left unprogrammed (U) or can be programmed(P) to obtain the additional features listed in the following table.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched duringreset. If the device is powered up without a reset, the latch initializes to a random value andholds that value until reset is activated. The latched value of EA must agree with the currentlogic level at that pin in order for the device to function properly.Programming