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1、西雅圖視頻機器人使用手冊 本 科 生 畢 業(yè) 論 文（外文翻譯） 譯文名稱： MCS -51系列單片機的功能和結(jié)構 專 業(yè)： 自動化 班 次： 學 員： 指導教員： 評 閱 人： 完成時間：2010年11月30 日

2、 海軍大連艦艇學院本科生外文翻譯 第14頁 Seattle Robotics CMUcam1 AppMod TM Vision System for BoeBot’s user guide Structure and function of the MCS-51 series Structure and function of the MCS-51 series one-chip computer is a name of a piece of one-chip computer series which Intel

3、 Company produces. This company introduced 8 top-grade one-chip computers of MCS-51 series in 1980 after introducing 8 one-chip computers of MCS-48 series in 1976. It belong to a lot of kinds this line of one-chip computer the chips have,such as 8051, 8031, 8751, 80C51BH, 80C31BH,etc., their basic c

4、omposition, basic performance and instruction system are all the same. 8051 daily representatives- 51 serial one-chip computers . An one-chip computer system is made up of several following parts: ( 1) One microprocessor of 8 (CPU). ( 2) At slice data memory RAM (128B/256B),it use not depositti

5、ng not can reading /data that write, such as result not middle of operation, final result and data wanted to show, etc. ( 3) Procedure memory ROM/EPROM (4KB/8KB ), is used to preserve the procedure , some initial data and form in slice. But does not take ROM/EPROM within some one-chip computers, suc

6、h as 8031 , 8032, 80C ,etc.. ( 4) Four 8 run side by side I/O interface P0 four P3, each mouth can use as introduction , may use as exporting too. ( 5) Two timer / counter, each timer / counter may set up and count in the way, used to count to the external incident, can set up into a timing way too,

7、 and can according to count or result of timing realize the control of the computer. ( 6) Five cut off cutting off the control system of the source . ( 7) One all duplexing serial I/O mouth of UART (universal asynchronous receiver/transmitter (UART) ), is it realize one-chip computer or one-chip com

8、puter and serial communication of computer to use for. ( 8) Stretch oscillator and clock produce circuit, quartz crystal finely tune electric capacity need outer. Allow oscillation frequency as 12 megahertas now at most. Every the above-mentioned part was joined through the inside data bus .Among th

9、em, CPU is a core of the one-chip computer, it is the control of the computer and command centre, made up of such parts as arithmetic unit and controller , etc.. The arithmetic unit can carry on 8 persons of arithmetic operation and unit ALU of logic operation while including one, the 1 storing devi

10、ce temporarilies of 8, storing device 2 temporarily, 8s accumulation device ACC, register B and procedure state register PSW, etc. Person who accumulate ACC count by 2 input ends entered of checking etc. temporarily as one operation often, come from person who store 1 operation is it is it make oper

11、ation to go on to count temporarily , operation result and loopback ACC with another one. In addition, ACC is often regarded as the transfer station of data transmission on 8051 inside . The same as general microprocessor, it is the busiest register. Help remembering that agreeing with A expresses i

12、n the order. The controller includes the procedure counter , the order is depositted, the order decipher, the oscillator and timing circuit, etc. The procedure counter is made up of counter of 8 for two, amounts to 16. It is a byte address counter of the procedure in fact, the content is the next IA

13、 that will carried out in PC. The content which changes it can change the direction that the procedure carries out . Shake the circuit in 8051 one-chip computers, only need outer quartz crystal and frequency to finely tune the electric capacity, its frequency range is its 12MHZ of 1.2MHZ. This pulse

14、 signal, as 8051 basic beats of working, namely the minimum unit of time. 8051 is the same as other computers, the work in harmony under the control of the basic beat, just like an orchestra according to the beat play that is commanded. There are ROM (procedure memory , can only read ) and RAM i

15、n 8051 slices (data memory, can is it can write ) two to read, they have each independent memory address space, dispose way to be the same with general memory of computer. Procedure 8051 memory and 8751 slice procedure memory capacity 4KB, address begin from 0000H, used for preserving the procedure

16、and form constant. Data 8051- 8751 8031 of memory data memory 128B, address false 00FH, use for middle result to deposit operation, the data are stored temporarily and the data are buffered etc.. In RAM of this 128B, there is unit of 32 byteses that can be appointed as the job register, this and gen

17、eral microprocessor is different, 8051 slice RAM and job register rank one formation the same to arrange the location. It is not very the same that the memory of MCS-51 series one-chip computer and general computer disposes the way in addition. General computer for first address space, ROM and RAM c

18、an arrange in different space within the range of this address at will, namely the addresses of ROM and RAM, with distributing different address space in a formation. While visiting the memory, corresponding and only an address Memory unit, can ROM, it can be RAM too, and by visiting the order simil

19、arly. This kind of memory structure is called the structure of Princeton. 8051 memories are divided into procedure memory space and data memory space on the physics structure, there are four memory spaces in all: The procedure stores in one and data memory space outside data memory and one in proced

20、ure memory space and one outside one, the structure forms of this kind of procedure device and data memory separated form data memory, called Harvard structure. But use the angle from users, 8051 memory address space is divided into three kinds: (1) In the slice, arrange blocks of FFFFH , 0000H of l

21、ocation , in unison outside the slice (use 16 addresses). (2) The data memory address space outside one of 64KB, the address is arranged from 0000H 64KB FFFFH (with 16 addresses ) too to the location. (3) Data memory address space of 256B (use 8 addresses). Three above-mentioned memory space address

22、es overlap, for distinguishing and designing the order symbol of different data transmission in the instruction system of 8051: CPU visit slice, ROM order spend MOVC , visit block RAM order uses MOVX outside the slice, RAM order uses MOV to visit in slice. 8051 one-chip computer have four 8 walk

23、 abreast I/O port, call P0, P1, P2 and P3. Each port is 8 accurate two-way mouths, accounts for 32 pins altogether. Every one I/O line can be used as introduction and exported independently. Each port includes a latch (namely special function register ), one exports the driver and a introduction buf

24、fer . Make data can latch when outputting, data can buffer when making introduction , but four function of passway these self-same. Expand among the system of memory outside having slice, four port these may serve as accurate two-way mouth of I/O in common use. Expand among the system of memory outs

25、ide having slice, P2 mouth see high 8 address off; P0 mouth is a two-way bus, send the introduction of 8 low addresses and data / export in timesharing The circuit of 8051 one-chip computers and four I/O ports is very ingenious in design. Familiar with I/O port logical circuit, not only help to us

26、e ports correctly and rationally, and will inspire to designing the peripheral logical circuit of one-chip computer to some extent. Load ability and interface of port have certain requirement, because output grade, P0 of mouth and P1 end output, P3 of mouth grade different at structure, so, the load

27、 ability and interface of its door demand to have nothing in common with each other. P0 mouth is different from other mouths, its output grade draws the resistance supremly. When using it as the mouth in common use to use, output grade is it leak circuit to turn on, is it is it urge NMOS draw the re

28、sistance on taking to be outer with it while inputting to go out to fail. When being used as introduction, should write "1" to a latch first. Every one with P0 mouth can drive 8 Model LS TTL load to export. P1 mouth is an accurate two-way mouth too, used as I/O in common use. Different from P0 mouth

29、 output of circuit its, draw load resistance link with power on inside have. In fact, the resistance is that two effects are in charge of FET and together: One FET is in charge of load, its resistance is regular. Another one can is it lead to work with close at two state, make its President resistan

30、ce value change approximate 0 or group value heavy two situation very. When it is 0 that the resistance is approximate , can draw the pin to the high level fast ; When resistance value is very large, P1 mouth, in order to hinder the introduction state high. Output as P1 mouth high electricity at ord

31、inary times, can is it draw electric current load to offer outwards, draw the resistance on neednt answer and thenning. Here when the port is used as introduction, must write into 1 to the corresponding latch first too, make FET end. Relatively about 20,000 ohms because of the load resistance in sce

32、ne and because 40,000 ohms, will not exert an influence on the data that are input. The structure of P2 some mouth is similar to P0 mouth, there are MUX switches. Is it similar to mouth partly to urge, but mouth large a conversion controls some than P1. P3 mouth one multi-functional port, mouth gett

33、ing many than P1 it have "and " 3 door and 4 buffer". Two part these, make her besides accurate two-way function with P1 mouth just, can also use the second function of every pin, "and " door 3 function one switch in fact, it determines to be to output data of latch to output second signal of functi

34、on. Act as W =At 1 oclock, output Q end signal; Act as Q =At 1 oclock, can output W line signal . At the time of programming, it is that the first function is still the second function but neednt have software that set up P3 mouth in advance . It hardware not inside is the automatic to have two func

35、tion outputted when CPU carries on SFR and seeks the location (the location or the byte ) to visit to P3 mouth /at not lasting lining, there are inside hardware latch Qs =1.The operation principle of P3 mouth is similar to P1 mouth. Output grade , P3 of mouth , P1 of P1 , connect with inside hav

36、e load resistance of drawing , every one of they can drive 4 Model LS TTL load to output. As while inputting the mouth, any TTL or NMOS circuit can drive P1 of 8051 one-chip computers as P3 mouth in a normal way . Because draw resistance on output grade of them have, can open a way collector too or

37、drain-source resistance is it urge to open a way, do not need to have the resistance of drawing outerly . Mouths are all accurate two-way mouths too. When the conduct is input, must write the corresponding port latch with 1 first . As to 80C51 one-chip computer, port can only offer milliampere of ou

38、tput electric currents, is it output mouth go when urging one ordinary basing of transistor to regard as, should contact a resistance among the port and transistor base , in order to the electricity while restraining the high level from exporting P1~P3 Being restored to the throne is the operation o

39、f initializing of an one-chip computer. Its main function is to turn PC into 0000H initially , make the one-chip computer begin to hold the conduct procedure from unit 0000H. Except that the ones that enter the system are initialized normally,as because procedure operate it make mistakes or operate

40、there arent mistake, in order to extricate oneself from a predicament , need to be pressed and restored to the throne the key restarting too. It is an input end which is restored to the throne the signal in 8051 China RST pin. Restore to the throne signal high level effective , should sustain 24 sha

41、ke cycle (namely 2 machine cycles ) the above its effective times. If 6 of frequency of utilization brilliant to shake, restore to the throne signal duration should exceed 4 delicate to finish restoring to the throne and operating. Produce the logic picture of circuit which is restored to the throne

42、 the signal: Restore to the throne the circuit and include two parts outside in the chip entirely. Outside that circuit produce to restore to the throne signal (RST ) hand over to Schmitts trigger, restore to the throne circuit sample to output , Schmitt of trigger constantly in each S5P2 , machine

43、 of cycle in having one more , then just got and restored to the throne and operated the necessary signal insidly. Restore to the throne resistance of circuit generally, electric capacity parameter suitable for 6 brilliant to shake, can is it restore to the throne signal high level duration greater

44、than 2 machine cycles to guarantee. Being restored to the throne in the circuit is simple, its function is very important. Pieces of one-chip computer system could normal running,should first check it can restore to the throne not succeeding. Checking and can pop ones head and monitor the pin with t

45、he oscillograph tentatively, push and is restored to the throne the key, the wave form that observes and has enough range is exported (instantaneous), can also through is it restore to the throne circuit group holding value carry on the experiment to change. MCS -51系列單片機的功能和結(jié)構 MCS - 51系列單片機具有一個

46、單芯片電腦的結(jié)構和功能，它是英特爾公司生產(chǎn)的系列產(chǎn)品的名稱。這家公司在1976年推出后，引進8位單芯片的MCS - 48系列計算機后于1980年推出的8位的MCS - 51系列單芯片計算機。諸如此類的單芯片電腦有很多種，如8051，8031，8751，80C51BH，80C31BH等，其基本組成，基本性能和指令系統(tǒng)都是相同的。 8051是51系列單芯片電腦的代表。 一個單芯片的計算機系統(tǒng)由以下幾個部分組成：（1）一個8位的微處理器（CPU）。（2）片內(nèi)數(shù)據(jù)存儲器RAM（128B/256B），它只讀/寫數(shù)據(jù)，如結(jié)果不在操作過程中，最終結(jié)果要顯示數(shù)據(jù)（3）程序存儲器ROM/ EPROM（4KB

47、/8KB），是用來保存程序，一些初步的數(shù)據(jù)和切片的形式。但一些單芯片電腦沒有考慮ROM / EPROM，如8031，8032，80C51等等。（4）4個8路運行的I / O接口，P0，P1,P2,P3，每口可以用作入口，也可以用作出口。 （5）兩個定時/計數(shù)器，每個定時/計數(shù)器可設置和計數(shù)的方式，用來計數(shù)外部事件，可以設置成定時方式也可以根據(jù)計算結(jié)果或定時控制實現(xiàn)計算機。 （6）5個中斷 （7）一個全雙工串行的I / UART（通用異步接收器I口/發(fā)送器（UART）），它是實現(xiàn)單芯片電腦或單芯片計算機和計算機的串行通信使用。 （8）振蕩器和時鐘產(chǎn)生電路，需要考慮石英晶體微調(diào)能力。允許振蕩頻率為

48、12MHz，每一個上述的部分都是通過內(nèi)部數(shù)據(jù)總線連接。其中CPU是一個芯片計算機的核心，它是計算機的指揮中心，是由算術單元和控制器等部分組成。算術單元可以進行8位算術運算和邏輯運算， ALU單元是其中一種運算器，1 8個存儲設備，暫存設備的積累設備進行協(xié)調(diào)，程序狀態(tài)寄存器PSW積累了2個輸入端的計數(shù)等檢查暫時作為一個操作往往由人來操作誰儲存1輸入的是它使操作去上暫時計數(shù)，另有一個操作的結(jié)果，回環(huán)協(xié)調(diào)。此外，協(xié)調(diào)往往是作為對8051內(nèi)的數(shù)據(jù)傳輸轉(zhuǎn)運站考慮。作為一般的微處理器，它是最繁忙的，幫助記住和同意與其的順序表示。該控制器包括程序計數(shù)器，解密的順序。振蕩器和定時電路等的程序計數(shù)器是一個由8個

49、計數(shù)器為2，總計 16位。這是一個字節(jié)的地址，其實程序計數(shù)器，是將在個人電腦內(nèi)進行。從而改變它的內(nèi)容可以改變方向的程序進行。在8051的單芯片電腦中的電路，只需要外部石英晶體和頻率微調(diào)電容，其頻率范圍為1.2MHz的其12MHz的。這種脈沖信號，作為8051的工作，即單位時間的最低基本節(jié)奏。 8051是其他電腦一樣，在拍控制的基本工作在和諧，就像一個管弦樂隊，根據(jù)擊敗發(fā)揮是指揮。 有光盤（程序存儲器，只能讀取），并在8051片（數(shù)據(jù)存儲器RAM，可以是可寫可讀，他們各自獨立的內(nèi)存地址空間，處理辦法是，與一般的電腦記憶體相同。 8051和8751的程序存儲器的存儲容量4KB的程序切片，地址開

50、始從0000H開始執(zhí)行，維護的程序和形式不斷使用。數(shù)據(jù)8051 - 8751的內(nèi)存數(shù)據(jù)存儲器128B條8031，地址虛假00FH，中層結(jié)果存入操作使用，數(shù)據(jù)存儲和數(shù)據(jù)是暫時緩沖等。在這128B條內(nèi)存，有32 字節(jié)，可以作為工作寄存器使用，這和一般的微處理器是不同的，8051片RAM和登記形成的同一級到安排的位置。這不是很相同的，MCS - 51系列內(nèi)存的單芯片計算機和通用計算機作主除了道路。通用計算機的第一個地址空間，ROM和RAM，可安排在不同的空間在這個范圍內(nèi)的地址范圍，即ROM和RAM地址的形成與分布在不同的地址空間。在訪問內(nèi)存，相應的，只有一個地址的內(nèi)存單元，可以用外部存儲，也可以內(nèi)存

51、，并通過訪問順序與此類似。這種內(nèi)存結(jié)構的一種被稱為普林斯頓結(jié)構。 8051記憶分為程序存儲器空間和數(shù)據(jù)存儲空間的物理結(jié)構上劃分，有四個在所有的記憶體空間：在1和數(shù)據(jù)外部數(shù)據(jù)存儲器和程序存儲器空間之一，一組在外面一個內(nèi)存空間的程序商店，結(jié)構這一種形式的程序和數(shù)據(jù)存儲器器件數(shù)據(jù)存儲器分開的形式，稱為哈佛結(jié)構。但是，從用戶使用，8051的內(nèi)存地址空間分為三種：分為（1）片內(nèi)，（使用16個地址一致的FFFFH，地點為0000H，塊）。 （2）64KB的外部數(shù)據(jù)存儲器空間的一個地址，該地址是從0000H開始執(zhí)行64KB的FFFFH安排16地址，也到該位置。 （3）數(shù)據(jù)存儲器的256B（使用8個地址）的地

52、址空間。上述三個內(nèi)存空間的地址重疊，區(qū)分和設計的8051指令系統(tǒng)中不同的數(shù)據(jù)傳輸順序代碼：CPU的訪問片，，訪問RAM塊順序使用MOVX指令外片，內(nèi)存為訪問片。 8051單芯片的電腦有4個8步行并進的I / O端口，分別為P0，P1，P2和P3。每個端口8位的雙向口，共占了32針。每一個I / O線可作為獨立的入口和出口。每個端口包括一個鎖存器（即特殊功能寄存器），1名入口和1出口引進緩沖區(qū)。使數(shù)據(jù)能鎖存輸出時，數(shù)據(jù)緩沖區(qū)時，可以引進，但4個通道這些自我相同的功能。系統(tǒng)中的內(nèi)存片展開外來的，這四個港口可作為準確的雙向的I /共同使用輸出口。系統(tǒng)的內(nèi)存中展開外來的片，P2口處于高位，8地址關

53、閉;入口P0口是雙向總線，發(fā)送地址和8個低數(shù)據(jù)。 8051單芯片電腦的4個I / O端口是非常巧妙的電路設計。熟悉I/ O端口的邏輯電路，不僅有助于正確和合理利用端口，并在一定程度上將有助于設計周邊的單芯片計算機的邏輯電路。在一定程度上負載能力和端口界面有一定的要求，因為輸出級，和P1口輸出端，P3口與P0口結(jié)構的不同，因此，負載能力和接口需求互相無太多共同之處。求解P0口是與其他口不同，它的輸出級提請阻力。當使用的常用是它的輸出級電路泄漏打開，它是利用它敦促采取NMOS管能與它外部的阻力，而輸入走出失敗。當被用作數(shù)據(jù)，應該寫“1”到內(nèi)部，每一個P0口與一個可以驅(qū)動8型號LS TT

54、L負載出口。P1口是一個準確的雙向口，共同使用輸出口。不同在P0口輸出的電路，得出與負載功率電阻內(nèi)有聯(lián)系。事實上，阻力是，兩個效果是在場效應管，共同負責：一個場效應管的負載負責，它的電阻是正常的。另一條是它可以導致在兩個工作狀態(tài)密切，使其電阻值變化近似0或2組值的情況非常嚴重。當它是0，該阻力是近似的，可以提請較快的高層次，當電阻值是非常大的，P1口以阻礙引進高電平。為P1口輸出高電平時，它是可以借鑒的負載提供電流向外，提請電阻無須回答。在這里，當端口作為引進使用，必須首先寫入1到相應的鎖存，使FET的結(jié)束。相對約20,000歐姆，因為在現(xiàn)場，因為負載電阻和40,000歐姆，不會產(chǎn)生對輸入的數(shù)

55、據(jù)的影響。一些為P2結(jié)構類似于P0口，有MUX的開關。它是類似口部分，大的一個轉(zhuǎn)換控制P1口的多功能端口，獲得第一位，這有很多“與”門和4個緩沖。兩部分，其中除了作出準確的雙向功能，還可以使用第二個函數(shù)的每一個針“與”門三功能開關，實際上，它決定將輸出數(shù)據(jù)鎖存到輸出的函數(shù)的第二個信號為W = 1點，輸出Q端信號。法令;法為Q = 1時時，可以輸出w線路信號，在制定方案的時侯，那就是第一個函數(shù)仍是第二個功能，但不必軟件預先設置P3口。IT硬件里面是不是有自動兩個函數(shù)輸出時的CPU進行SFR和要求的位置（位置或字節(jié)）來訪問，在沒有至P3口，里面有硬件鎖Q報表，P3口的工作原理類似于P1口。 輸

56、出級，P1，P3口連接內(nèi)帶的負載電阻的圖紙，每一個能驅(qū)動4型號LS TTL負載輸出1。由于輸入口，任何TTL或NMOS電路可以驅(qū)動8051的單芯片在一個正常的方式。因為他們利用輸出級阻力，可以打開漏源電阻以敦促打開方式，不需要有阻力。都是準確的雙向口。當行為是輸入，必須編寫相應的鎖存器。至于80C51的單芯片計算機，端口只能提供輸出毫安的電流，是它的輸出口去當一個普通的晶體管，要求應與端口之間和晶體管的基極電阻，以電而從出口限制P1?P3被恢復了的高水平，是一個單芯片電腦初始化操作。其主要功能是把最初的PC為0000H，使單芯片電腦開始持有單位0000H開始執(zhí)行程序的行為。唯一例外的是那些進入

57、系統(tǒng)初始化正常，程序操作，而是因為它犯了錯或沒有錯，為了擺脫自己的困境，需要按下和恢復位的按鍵鍵重新啟動了。這是一個輸入端是恢復位，在8051中國RST引腳信號?；謴臀坏男盘栠€原到高一級的有效值，應維持24倍以上的有效周期（即2個機器周期）。如果使用頻率6，恢復位的信號持續(xù)時間應超過4微妙完成恢復。設計的電路，恢復位的信號邏輯圖： 恢復位的電路和芯片包括兩個部分外完全。以外的電路產(chǎn)生恢復到施密特觸發(fā)了位信號（RST），恢復位電路示例輸出，施密特不斷在每個S5P2，觸發(fā)機循環(huán)，那么就得到了恢復位所需的信號。還原6電阻的電路一般，電容參數(shù)適合，它是可以恢復到較高水平的信號持續(xù)時間大于2個機器周期來

58、保證。作為恢復到電路，其功能是非常重要的。一個芯片的計算機系統(tǒng)能夠正常運轉(zhuǎn)，應先檢查它可不可以恢復。檢查可以彈出一個首部和監(jiān)測與示波器針暫定，推動并恢復位的關鍵，波形式觀察和有足夠的范圍是出口（瞬時），也可以通過它使恢復電路進行改變。 tgKQcWA3PtGZ7R4I30kA1DkaGhn3XtKknBYCUDxqA7FHYi2CHhI92tgKQcWA3PtGshLs50cLmTWN60eo8Wgqv7XAv2OHUm32WGeaUwYDIAWGMeR4I30kA1DkaGhn3XtKknBYCUDxqA7FHYi2CHhI92tgKQcWA3PtGZ7R4I30kA1DkaGtgKQc

59、WA3PtGZ7R4I30kA1DkaGhn3XtKknBYCUDxqA7FHYi2CHhI92tgKQcWA3PtGshLs50cLmTWN60eo8Wgqv7XAv2OHUm32WGeaUwYDIAWGMeR4I30kA1DkaGhn3XtKknBYCUDxqA7FHYi2CHhI92tgKQcWA3PtGZ7R4I30kA1DkaGtgKQcWA3PtGZ7R4I30kA1DkaGhn3XtKknBYCUDxqA7FHYi2CHhI92tgKQcWA3PtGshLs50cLmTWN60eo8Wgqv7XAv2OHUm32WGeaUwYDIAWGeR4I30kA1DkaGhn3XtKknB

60、YCUDxqA7FHYi2CHhI92tgKQcWA3PtGZ7R4I30kA1DkaGtgKQcWA3PtGZ7R4I30kA1DkaGhn3XtKknBYCUDxqA7FHYi2CHhI92tgKQcWA3PtGshLs50cLmTWN60eo8Wgqv7XAv2OHUm32WGeaUwYDIAWGMeR4I30kA1DkaGhn3XtKknBYCUDxqA7FHYi2CHhI92tgKQcWA3PtGZ7R4I30kA1DkaGtgKQcWA3PtGZ7R4I30kA1DkaGhn3XtKknBYCUDxqA7FHYi2CHhI92tgKQcWA3PtGshLs50cLmTWN60eo8Wgqv7XAv2OHUm32WGeaUwYDIAWGMeR4I30kA1DkaGhn3XtKknBYCUDxqA7FHYi2CHhI92tgKQcWA3PtGZ7R4I30kA1DkaGtgKQcWA3PtGZ7R4I30kA1DkaGhn3XtKknBYCUDxqA7FHYi2CHhI92tgKQcWA3PtGshLs50cLmTWN60eo8Wgqv7XAv2OHUm32WGeaUwYDIAWGMeR4I30kA1DkaGhn3XtKknBYCUDxqA7FHYi2CHhI92tgKQcWA3PtGZ7R4I30kA1DkaG 第12頁 海軍大連艦艇學院本科生譯文原文