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1、西安交通大學(xué)城市學(xué)院本科生畢業(yè)設(shè)計(jì)（論文） AT89C51外文翻譯 Description The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of Flash Programmable and Erasable Read Only Memory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with

2、 the industry standard MCS-51? instruction-set and pinout. The on-chip Flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer wh

3、ich provides a highly flexible and cost effective solution to many embedded control applications. Features ? Compatible with MCS-51? Products ? 4K Bytes of In-System Reprogrammable Flash Memory – Endurance: 1,000 Write/Erase Cycles ? Fully Static Operation: 0 Hz to 24 MHz ? Three-Level Program

4、 Memory Lock ? 128 x 8-Bit Internal RAM ? 32 Programmable I/O Lines ? Two 16-Bit Timer/Counters ? Six Interrupt Sources ? Programmable Serial Channel ? Low Power Idle and Power Down Modes The AT89C51 provides the following standard features: 4K bytes of Flash,128 bytes of RAM, 32 I/O lines, t

5、wo 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The I

6、dle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. VCC Supply voltage. GND Ground.

7、Port 0 Port 0 is an 8-bit open-drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs. Port 0 may also be configured to be the multiplexed low-order address/data bus during accesses to

8、 external program and data memory. In this mode P0 has internal pullups. Port 0 also receives the code bytes during Flash programming, and outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bi-directional I/O p

9、ort with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal

10、pullups.Port 1 also receives the low-order address bytes during Flash programming and verification. Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins they are pulled high by the inte

11、rnal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16

12、-bit addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some c

13、ontrol signals during Flash programming and verification. Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As

14、 inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT89C51 as listed below: Port 3 also receives some control signals for Flash programming and verification. RST Reset in

15、put. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE/PROG Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during Flash programming. In no

16、rmal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR lo

17、cation 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. Whe

18、n the AT89C51 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. EA/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch code

19、from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions.This pin also receives the 12-volt programming enable voltage (VPP) during Flash

20、programming, for parts that require 12-volt VPP. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier.Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively,of an in

21、verting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2.There are no requ

22、irements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Idle Mode In idle mode, the CPU puts itself to sleep while all the o

23、n-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminate

24、d by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the po

25、ssibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Figure 1. Oscillator Connections Note: C1, C2 = 30 pF 10 pF for Crystals= 40 pF 10 pF for Ce

26、ramic Resonators Figure 2. External Clock Drive Configuration Power-down Mode In the power-down mode, the oscillator is stopped, and the instruction that invokes power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power-d

27、own mode is terminated. The only exit from power-down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and s

28、tabilize. Program Memory Lock Bits On the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below.When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the devic

29、e is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Programming the Flash The

30、AT89C51 is normally shipped with the on-chip Flash memory array in the erased state (that is, contents = FFH)and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low-voltage programming mode provides a conveni

31、ent way to program the AT89C51 inside the user’s system, while the high-voltage programming mode is compatible with conventional thirdparty Flash or EPROM programmers.The AT89C51 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and devi

32、ce signature codes are listed in the following table. The AT89C51 code memory array is programmed byte-by-byte in either programming mode. To program any non-blank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programmi

33、ng the AT89C51, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the AT89C51, take the following steps. 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data line

34、s. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timedand typically takes no more than 1.5 ms. Repeat steps 1 throug

35、h 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The AT89C51 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the writte

36、n datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4

37、is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification.

38、The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Chip Erase: The entire Flash array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is w

39、ritten with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logi

40、c low. The values returned are as follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51 (032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming Programming Interface Every code byte in the Flash array can be written and the entire array can

41、 be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion. All major programming vendors offer worldwide support for the Atmel microcontroller series. Please contact your local programm

42、ing vendor for the appropriate software revision. Flash Programming and Verification Waveforms - High-voltage Mode (VPP = 12V) Flash Programming and Verification Waveforms - Low-voltage Mode (VPP = 5V) Flash Programming and Verification Characteristics TA = 0C to 70C, VCC = 5.0 10%

43、 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of t

44、his specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = -40C to 85C, VCC = 5.0V 20% (unless otherwise noted) Notes: 1. Under steady state (non-transient) conditions, IOL must be externally lim

45、ited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the list

46、ed test conditions. 2. Minimum VCC for Power-down is 2V. AC Characteristics Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF. External Program and Data Memory Characteristics External Program Memory Read Cyc

47、le External Data Memory Read Cycle External Data Memory Write Cycle External Clock Drive Waveforms External Clock Drive Serial Port Timing: Shift Register Mode Test Conditions (VCC = 5.0 V 20%; Load Capacitance = 80 pF) Shift Register Mode Timing Waveforms AC Testing Input/Ou

48、tput Waveforms(1) Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0.Float Waveforms(1) Note: 1. For timing purposes, a port pin is no longer floating when a 100mV c

49、hange from load voltage occurs. A port pin begins to float when 100mV change from the loaded VOH/VOL level occurs. AT89C51中文原文 AT89C51是美國(guó)ATMEL公司生產(chǎn)的低電壓，高性能CMOS8位單片機(jī)，片內(nèi)含4k bytes的可反復(fù)擦寫的只讀程序存儲(chǔ)器（PEROM）和128 bytes的隨機(jī)存取數(shù)據(jù)存儲(chǔ)器（RAM），器件采用ATMEL公司的高密度、非易失性存儲(chǔ)技術(shù)生產(chǎn)，兼容標(biāo)準(zhǔn)MCS-51指令系統(tǒng)，片內(nèi)置通用8位中

50、央處理器（CPU）和Flash存儲(chǔ)單元，功能強(qiáng)大AT89C51單片機(jī)可為您提供許多高性價(jià)比的應(yīng)用場(chǎng)合，可靈活應(yīng)用于各種控制領(lǐng)域。 主要性能參數(shù)： 與MCS-51產(chǎn)品指令系統(tǒng)完全兼容 4k字節(jié)可重擦寫Flash閃速存儲(chǔ)器 1000次擦寫周期 全靜態(tài)操作：0Hz－24MHz 三級(jí)加密程序存儲(chǔ)器 1288字節(jié)內(nèi)部RAM 32個(gè)可編程I／O口線 2個(gè)16位定時(shí)／計(jì)數(shù)器 6個(gè)中斷源 可編程串行UART通道 低功耗空閑和掉電模式 功能特性概述： AT89C51 提供以下標(biāo)準(zhǔn)功能：4k 字節(jié)Flash 閃速存儲(chǔ)器，128字節(jié)內(nèi)部RAM，32 個(gè)I／O 口線，兩個(gè)16位定時(shí)／計(jì)數(shù)器

51、，一個(gè)5向量?jī)杉?jí)中斷結(jié)構(gòu)，一個(gè)全雙工串行通信口，片內(nèi)振蕩器及時(shí)鐘電路。同時(shí)，AT89C51可降至0Hz的靜態(tài)邏輯操作，并支持兩種軟件可選的節(jié)電工作模式?？臻e方式停止CPU的工作，但允許RAM，定時(shí)／計(jì)數(shù)器，串行通信口及中斷系統(tǒng)繼續(xù)工作。掉電方式保存RAM中的內(nèi)容，但振蕩器停止工作并禁止其它所有部件工作直到下一個(gè)硬件復(fù)位。 引腳功能說明 Vcc：電源電壓 GND：地 P0 口：P0 口是一組8 位漏極開路型雙向I／O 口，也即地址／數(shù)據(jù)總線復(fù)用口。作為輸出口用時(shí)，每位能吸收電流的方式驅(qū)動(dòng)8個(gè)TTL邏輯門電路，對(duì)端口寫“1”可作為高阻抗輸入端用。在訪問外部數(shù)據(jù)存儲(chǔ)器或

52、程序存儲(chǔ)器時(shí)，這組口線分時(shí)轉(zhuǎn)換地址（低8位）和數(shù)據(jù)總線復(fù)用，在訪問期間激活內(nèi)部上拉電阻。 在FIash編程時(shí)，P0口接收指令字節(jié)，而在程序校驗(yàn)時(shí)，輸出指令字節(jié)，校驗(yàn)時(shí)，要求外接上拉電阻。 P1口：P1是一個(gè)帶內(nèi)部上拉電阻的8位雙向I／O口，P1的輸出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4個(gè)TTL邏輯 門電路。對(duì)端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口。作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。FIash編程和程序校驗(yàn)期間，P1接收低8位地址。 P2口：P2是一個(gè)帶有內(nèi)部上拉電阻的8位雙向I／O口，P2的輸出緩沖級(jí)可驅(qū)動(dòng)（吸

53、收或輸出電流）4個(gè)TTL邏輯門電路。對(duì)端口寫“1”，通過內(nèi)部的上拉電阻把端口拉到高電平，此時(shí)可作輸入口，作輸入口使用時(shí)，因?yàn)閮?nèi)部存在上拉電阻，某個(gè)引腳被外部信號(hào)拉低時(shí)會(huì)輸出一個(gè)電流（IIL）。在訪問外部程序存儲(chǔ)器或16位地址的外部數(shù)據(jù)存儲(chǔ)器（例如執(zhí)行MOVX@DPTR指令）時(shí)，P2口送出高8位地址數(shù)據(jù)。在訪問8 位地址的外部數(shù)據(jù)存儲(chǔ)器（如執(zhí)行MOVX@RI 指令）時(shí)，P2 口線上的內(nèi)容（也即特殊功能寄存器（SFR）區(qū)中R2寄存器的內(nèi)容），在整個(gè)訪問期間不改變。 Flash編程或校驗(yàn)時(shí)，P2亦接收高位地址和其它控制信號(hào)。 P3口：P3口是一組帶有內(nèi)部上拉電阻的8 位雙向I／O 口。P3 口輸

54、出緩沖級(jí)可驅(qū)動(dòng)（吸收或輸出電流）4 個(gè)TTL邏輯門電路。對(duì)P3 口寫入“1”時(shí)，它們被內(nèi)部上拉電阻拉高并可作為輸入端口。作輸入端時(shí)，被外部拉低的P3 口將用上拉電阻輸出電流（IIL）。P3口除了作為一般的I／O口線外，更重要的用途是它的第二功能，如下表所示： P3口還接收一些用于Flash閃速存儲(chǔ)器編程和程序校驗(yàn)的控制信號(hào)。 RST：復(fù)位輸入。當(dāng)振蕩器工作時(shí)，RST引腳出現(xiàn)兩個(gè)機(jī)器周期以上高電平將使單片機(jī)復(fù)位。 ALE／PROG： 當(dāng)訪問外部程序存儲(chǔ)器或數(shù)據(jù)存儲(chǔ)器時(shí)，ALE（地址鎖存允許）輸出脈沖用于鎖存地址的低8位字節(jié)。即使不訪問外部存儲(chǔ)器，ALE 仍以時(shí)鐘振蕩頻率的l／6 輸出固

55、定的正脈沖信號(hào)，因此它可對(duì)外輸出時(shí)鐘或用于定時(shí)目的。要注意的是：每當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器時(shí)將跳過一個(gè)ALE脈沖。對(duì)Flash存儲(chǔ)器編程期間，該引腳還用于輸入編程脈沖（PROG）。如有必要，可通過對(duì)特殊功能寄存器（SFR）區(qū)中的8EH單元的DO 位置位，可禁止ALE 操作。該位置位后，只有一條MOVX和MOVC指令A(yù)LE才會(huì)被激活。此外，該引腳會(huì)被微弱拉高，單片機(jī)執(zhí)行外部程序時(shí)，應(yīng)設(shè)置ALE無效。 PSEN：程序儲(chǔ)存允許（PSEN）輸出是外部程序存儲(chǔ)器的讀選通信號(hào)，當(dāng)AT89C51 由外部程序存儲(chǔ)器取指令（或數(shù)據(jù)）時(shí)，每個(gè)機(jī)器周期兩次PSEN有效，即輸出兩個(gè)脈沖。在此期間，當(dāng)訪問外部數(shù)據(jù)存儲(chǔ)器，

56、這兩次有效的PSEN信號(hào)不出現(xiàn)。 EA／VPP：外部訪問允許。欲使CPU僅訪問外部程序存儲(chǔ)器（地址為0000H—FFFFH），EA端必須保持低電平（接地）。需注意的是：如果加密位LB1被編程，復(fù)位時(shí)內(nèi)部會(huì)鎖存EA端狀態(tài)。如EA端為高電平（接VCC端），CPU則執(zhí)行內(nèi)部程序存儲(chǔ)器中的指令。Flash存儲(chǔ)器編程時(shí)，該引腳加上+12V的編程允許電源Vpp，當(dāng)然這必須是該器件是使用12V編程電壓Vpp。 XTAL1：振蕩器反相放大器的及內(nèi)部時(shí)鐘發(fā)生器的輸入端。 XTAL2：振蕩器反相放大器的輸出端。 時(shí)鐘振蕩器：AT89C5l 中有一個(gè)用于構(gòu)成內(nèi)部振蕩器的高增益反相放大器，引腳XTAL1 和X

57、TAL2 分別是該放大器的輸入端和輸出端。這個(gè)放大器與作為反饋元件的片外石英晶體或陶瓷諧振器一起構(gòu)成自激振蕩器，振蕩電路參見圖5。外接石英晶體（或陶瓷諧振器）及電容C1、C2接在放大器的反饋回路中構(gòu)成并聯(lián)振蕩電路。對(duì)外接電容C1、C2雖然沒有十分嚴(yán)格的要求，但電容容量的大小會(huì)輕微影響振蕩頻率的高低、振蕩器工作的穩(wěn)定性、起振的難易程序及溫度穩(wěn)定性，如果使用石英晶體，我們推薦電容使用30pF10pF，而如使用陶瓷諧振器建議選擇40pF10F。用戶也可以采用外部時(shí)鐘。采用外部時(shí)鐘的電路如圖5右圖所示。這種情況下，外部時(shí)鐘脈沖接到XTAL1端，即內(nèi)部時(shí)鐘發(fā)生器的輸入端，XTAL2則懸空。由于外部時(shí)鐘信

58、號(hào)是通過一個(gè)2分頻觸發(fā)器后作為內(nèi)部時(shí)鐘信號(hào)的，所以對(duì)外部時(shí)鐘信號(hào)的占空比沒有特殊要求，但最小高電平持續(xù)時(shí)間和最大的低電平持續(xù)時(shí)間應(yīng)符合產(chǎn)品技術(shù)條件的要求。 空閑節(jié)電模式： AT89C51 有兩種可用軟件編程的省電模式，它們是空閑模式和掉電工作模式。這兩種方式是控制專用寄存器PCON（即電源控制寄存器）中的PD（PCON.1）和IDL（PCON.0）位來實(shí)現(xiàn)的。PD 是掉電模式，當(dāng)PD=1 時(shí)，激活掉電工作模式，單片機(jī)進(jìn)入掉電工作狀態(tài)。IDL是空閑等待方式，當(dāng)IDL=1，激活空閑工作模式，單片機(jī)進(jìn)入睡眠狀態(tài)。如需同時(shí)進(jìn)入兩種工作模式，即PD和IDL同時(shí)為1，則先激活掉電模式。 在空閑工作模

59、式狀態(tài)，CPU保持睡眠狀態(tài)而所有片內(nèi)的外設(shè)仍保持激活狀態(tài)，這種方式由軟件產(chǎn)生。此時(shí)，片內(nèi)RAM和所有特殊功能寄存器的內(nèi)容保持不變?？臻e模式可由任何允許的中斷請(qǐng)求或硬件復(fù)位終止。 終止空閑工作模式的方法有兩種，其一是任何一條被允許中斷的事件被激活，IDL（PCON.0）被硬件清除，即刻終止空閑工作模式。程序會(huì)首先響應(yīng)中斷，進(jìn)入中斷服務(wù)程序，執(zhí)行完中斷服務(wù)程序并緊隨RETI（中斷返回）指令后，下一條要執(zhí)行的指令就是使單片機(jī)進(jìn)入空閑模式那條指令后面的一條指令。 其二是通過硬件復(fù)位也可將空閑工作模式終止。需要注意的是，當(dāng)由硬件復(fù)位來終止空閑工作模式時(shí)，CPU 通常是從激活空閑模式那條指令的下一條指

60、令開始繼續(xù)執(zhí)行程序的，要完成內(nèi)部復(fù)位操作，硬件復(fù)位脈沖要保持兩個(gè)機(jī)器周期（24個(gè)時(shí)鐘周期）有效，在這種情況下，內(nèi)部禁止CPU訪問片內(nèi)RAM，而允許訪問其它端口。為了避免可能對(duì)端口產(chǎn)生意外寫入，激活空閑模式的那條指令后一條指令不應(yīng)是一條對(duì)端口或外部存儲(chǔ)器的寫入指令。 掉電模式： 在掉電模式下，振蕩器停止工作，進(jìn)入掉電模式的指令是最后一條被執(zhí)行的指令，片內(nèi)RAM 和特殊功能寄存器的內(nèi)容在終止掉電模式前被凍結(jié)。退出掉電模式的唯一方法是硬件復(fù)位，復(fù)位后將重新定義全部特殊功能寄存器但不改變RAM中的內(nèi)容，在Vcc恢復(fù)到正常工作電平前，復(fù)位應(yīng)無效，且必須保持一定時(shí)間以使振蕩器重啟動(dòng)并穩(wěn)定工作。 空閑

61、和掉電模式外部引腳狀態(tài) 程序存儲(chǔ)器的加密： AT89C51 可使用對(duì)芯片上的3 個(gè)加密位LB1、LB2、LB3 進(jìn)行編程（P）或不編程（U）來得到如下表所示的功能加 密位保護(hù)功能表： 注：表中的U — 表示未編程，P — 表示編程 當(dāng)加密位LB1 被編程時(shí)，在復(fù)位期間，EA端的邏輯電平被采樣并鎖存，如果單片機(jī)上電后一直沒有復(fù)位，則鎖存起的初始值是一個(gè)隨機(jī)數(shù)，且這個(gè)隨機(jī)數(shù)會(huì)一直保存到真正復(fù)位為止。為使單片機(jī)能正常工作，被鎖存的EA 電平值必須與該引腳當(dāng)前的邏輯電平一致。此外，加密位只能通過整片擦除的方法清除。 Flash閃速存儲(chǔ)器的編程： AT89C51 單片機(jī)內(nèi)部有4k

62、字節(jié)的Flash PEROM，這個(gè)Flash 存儲(chǔ)陣列出廠時(shí)已處于擦除狀態(tài)（即所有存儲(chǔ)單元的內(nèi)容均為FFH），用戶隨時(shí)可對(duì)其進(jìn)行編程。編程接口可接收高電壓（+12V）或低電壓（Vcc）的允許編程信號(hào)。低電壓編程模式適合于用戶在線編程系統(tǒng)，而高電壓編程模式可與通用EPROM編程器兼容。 AT89C51單片機(jī)中，有些屬于低電壓編程方式，而有些則是高電壓編程方式，用戶可從芯片上的型號(hào)和讀取芯片內(nèi)的名字節(jié)獲得該信息，見下表。 AT89C51的程序存儲(chǔ)器陣列是采用字節(jié)寫入方式編程的，每次寫入一個(gè)字節(jié)，要對(duì)整個(gè)芯片內(nèi)的PEROM程序存儲(chǔ)器寫入一個(gè)非空字節(jié)，必須使用片擦除的方式將整個(gè)存儲(chǔ)器的內(nèi)容清除

63、。 編程方法： 編程前，須按表6和圖6所示設(shè)置好地址、數(shù)據(jù)及控制信號(hào)。編程單元的地址加在P1口和P2口的P2.0－P2.3（11位地址范圍為0000H－0FFFH），數(shù)據(jù)從P0口輸入，引腳P2.6、P2.7和P3.6、P3.7的電平設(shè)置見表6，PSEN為低電平，RST保持高電平，EA／Vpp 引腳是編程電源的輸入端，按要求加上編程電壓，ALE／PROG引腳輸入編程脈沖（負(fù)脈沖）。編程時(shí)，可采用4－20MHz的時(shí)鐘振蕩器，AT89C51編程方法如下： 1．在地址線上加上要編程單元的地址信號(hào)。 2．在數(shù)據(jù)線上加上要寫入的數(shù)據(jù)字節(jié)。 3．激活相應(yīng)的控制信號(hào)。 4．在高電壓編程方式時(shí)，將E

64、A／Vpp端加上+12V編程電壓。 5．每對(duì)Flash存儲(chǔ)陣列寫入一個(gè)字節(jié)或每寫入一個(gè)程序加密位，加上一個(gè)ALE／PROG編程脈沖。改變編程單元的地址和寫入的數(shù)據(jù)，重復(fù)1—5步驟，直到全部文件編程結(jié)束。每個(gè)字節(jié)寫入周期是自身定時(shí)的，通常約為1.5ms。 數(shù)據(jù)查詢： AT89C51單片機(jī)用數(shù)據(jù)查詢方式來檢測(cè)一個(gè)寫周期是否結(jié)束，在一個(gè)寫周期中，如需讀取最后寫入的那個(gè)字節(jié)，則讀出的數(shù)據(jù)的最高位（P0.7）是原來寫入字節(jié)最高位的反碼。寫周期完成后，有效的數(shù)據(jù)就會(huì)出現(xiàn)在所有輸出端上，此時(shí)，可進(jìn)入下一個(gè)字節(jié)的寫周期，寫周期開始后，可在任意時(shí)刻進(jìn)行數(shù)據(jù)查詢。 Ready／Busy：字節(jié)編程的進(jìn)度可通

65、過RDY／BSY輸出信號(hào)監(jiān)測(cè)，編程期間，ALE變?yōu)楦唠娖健癏”后P3.4（RDY ／BSY）端電平被拉低，表示正在編程狀態(tài)（忙狀態(tài)）。編程完成后，P3.4變?yōu)楦唠娖奖硎緶?zhǔn)備就緒狀態(tài)。 程序校驗(yàn)：如果加密位LB1、LB2沒有進(jìn)行編程，則代碼數(shù)據(jù)可通過地址和數(shù)據(jù)線讀回原編寫的數(shù)據(jù)，采用下圖的電路，程序存儲(chǔ)器的地址由P1 和P2 口的P2.0－P2.3輸入，數(shù)據(jù)由P0口讀出，P2.6、P2.7和P3.6、P3.7的控制信號(hào)見表6，PSEN保持低電平，ALE、EA和RST保持高電平。校驗(yàn)時(shí)，P0口須接上10k左右的上拉電阻。 表6 Flash 存儲(chǔ)器編程真值表 注：片擦除操作時(shí)要求PROG

66、脈沖寬度為10ms 圖5編程電路 圖6校驗(yàn)電路 加密位不可直接校驗(yàn)，加密位的校驗(yàn)可通過對(duì)存儲(chǔ)器的校驗(yàn)和寫入狀態(tài)來驗(yàn)證。 Flash存儲(chǔ)器編程和校驗(yàn)時(shí)序圖7（高電壓編程）和圖8（低電壓編程）。 Flash存儲(chǔ)器編程和校驗(yàn)的波形時(shí)序（高電壓編程VPP=12V） Flash存儲(chǔ)器編程和校驗(yàn)的波形時(shí)序（低電壓編程VPP=5V） 芯片擦除：利用控制信號(hào)的正確組合（表6）并保持ALE／PROG引腳10mS 的低電平脈沖寬度即可將PEROM 陣 列（4k字節(jié)）和三個(gè)加密位整片擦除，代碼陣列在片擦除操作中將任何非空單元寫入“1”，這步驟需再編程之前進(jìn)行。 讀片內(nèi)簽名字節(jié)：AT89C51 單片機(jī)內(nèi)有3 個(gè)簽名字節(jié)，地址為030H、031H 和032H。用于聲明該器件的廠商、型號(hào)和編程電壓。讀簽名字節(jié)的過程和單元030H、031H及032H的正常校驗(yàn)相仿，只需將